{"id":"https://openalex.org/W1972621490","doi":"https://doi.org/10.1109/recosoc.2014.6861352","title":"An application scenario for dynamically reconfigurable FPGAs","display_name":"An application scenario for dynamically reconfigurable FPGAs","publication_year":2014,"publication_date":"2014-05-01","ids":{"openalex":"https://openalex.org/W1972621490","doi":"https://doi.org/10.1109/recosoc.2014.6861352","mag":"1972621490"},"language":"en","primary_location":{"id":"doi:10.1109/recosoc.2014.6861352","is_oa":false,"landing_page_url":"https://doi.org/10.1109/recosoc.2014.6861352","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5071062106","display_name":"Fynn Schwiegelshohn","orcid":"https://orcid.org/0000-0002-3044-576X"},"institutions":[{"id":"https://openalex.org/I904495901","display_name":"Ruhr University Bochum","ror":"https://ror.org/04tsk2644","country_code":"DE","type":"education","lineage":["https://openalex.org/I904495901"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Fynn Schwiegelshohn","raw_affiliation_strings":["Ruhr-Universitat Bochum, Bochum, Nordrhein-Westfalen, DE","Embedded Syst. of Inf. Technol., Ruhr-Univ. Bochum, Bochum, Germany"],"affiliations":[{"raw_affiliation_string":"Ruhr-Universitat Bochum, Bochum, Nordrhein-Westfalen, DE","institution_ids":["https://openalex.org/I904495901"]},{"raw_affiliation_string":"Embedded Syst. of Inf. Technol., Ruhr-Univ. Bochum, Bochum, Germany","institution_ids":["https://openalex.org/I904495901"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5108437484","display_name":"Michael H\u00fcbner","orcid":"https://orcid.org/0000-0003-3785-7959"},"institutions":[{"id":"https://openalex.org/I904495901","display_name":"Ruhr University Bochum","ror":"https://ror.org/04tsk2644","country_code":"DE","type":"education","lineage":["https://openalex.org/I904495901"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Michael Hubner","raw_affiliation_strings":["Ruhr-Universitat Bochum, Bochum, Nordrhein-Westfalen, DE","Embedded Syst. of Inf. Technol., Ruhr-Univ. Bochum, Bochum, Germany"],"affiliations":[{"raw_affiliation_string":"Ruhr-Universitat Bochum, Bochum, Nordrhein-Westfalen, DE","institution_ids":["https://openalex.org/I904495901"]},{"raw_affiliation_string":"Embedded Syst. of Inf. Technol., Ruhr-Univ. Bochum, Bochum, Germany","institution_ids":["https://openalex.org/I904495901"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5071062106"],"corresponding_institution_ids":["https://openalex.org/I904495901"],"apc_list":null,"apc_paid":null,"fwci":1.8389,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.8430016,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"1","issue":null,"first_page":"1","last_page":"8"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8814562559127808},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7740970849990845},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.6930490732192993},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.5853580832481384},{"id":"https://openalex.org/keywords/robot","display_name":"Robot","score":0.5400856733322144},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4392596483230591},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3672798275947571},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.21986114978790283},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.07571950554847717}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8814562559127808},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7740970849990845},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.6930490732192993},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.5853580832481384},{"id":"https://openalex.org/C90509273","wikidata":"https://www.wikidata.org/wiki/Q11012","display_name":"Robot","level":2,"score":0.5400856733322144},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4392596483230591},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3672798275947571},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.21986114978790283},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.07571950554847717}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/recosoc.2014.6861352","is_oa":false,"landing_page_url":"https://doi.org/10.1109/recosoc.2014.6861352","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":26,"referenced_works":["https://openalex.org/W1520175292","https://openalex.org/W1970026646","https://openalex.org/W1979566015","https://openalex.org/W1982819660","https://openalex.org/W1985856855","https://openalex.org/W2011039300","https://openalex.org/W2017661493","https://openalex.org/W2040176884","https://openalex.org/W2073133456","https://openalex.org/W2074231493","https://openalex.org/W2075137135","https://openalex.org/W2077749405","https://openalex.org/W2092046673","https://openalex.org/W2097090706","https://openalex.org/W2123412205","https://openalex.org/W2125827767","https://openalex.org/W2132929529","https://openalex.org/W2140311411","https://openalex.org/W2161577181","https://openalex.org/W2164423474","https://openalex.org/W2177274602","https://openalex.org/W4230687063","https://openalex.org/W4232496889","https://openalex.org/W4240447695","https://openalex.org/W6631025532","https://openalex.org/W6646091540"],"related_works":["https://openalex.org/W1612076744","https://openalex.org/W2152074211","https://openalex.org/W2126857316","https://openalex.org/W2129019972","https://openalex.org/W3164085601","https://openalex.org/W1967938402","https://openalex.org/W1522032972","https://openalex.org/W2139962137","https://openalex.org/W2113308450","https://openalex.org/W2386041993"],"abstract_inverted_index":{"Several":[0],"recent":[1],"studies":[2],"have":[3],"shown":[4],"the":[5,25,62,66,81,91,111,117,121],"technological":[6],"feasibility":[7],"of":[8,27,65,124],"dynamically":[9,76],"reconfigurable":[10,77],"field":[11],"programmable":[12],"gate":[13],"arrays":[14],"(FPGA).":[15],"In":[16,90],"this":[17,33],"paper,":[18],"we":[19,70],"introduce":[20],"an":[21,44],"application":[22],"scenario":[23],"from":[24,32],"area":[26],"autonomous":[28,45],"robots":[29],"which":[30,60],"benefits":[31],"technology":[34],"as":[35],"it":[36],"uses":[37],"elastic":[38,58],"algorithms.":[39],"The":[40],"processing":[41],"unit":[42],"in":[43,113],"robot":[46],"must":[47],"handle":[48],"localization,":[49],"cognition,":[50],"motion":[51],"control,":[52],"and":[53,86],"perception.":[54],"We":[55],"analyze":[56],"several":[57,84],"algorithms":[59],"solve":[61],"different":[63],"tasks":[64,112],"proposed":[67],"application.":[68],"Additionally,":[69],"suggest":[71],"a":[72,130],"design":[73],"methodology":[74],"for":[75],"FPGAs":[78],"that":[79],"divides":[80],"problem":[82],"into":[83],"steps":[85],"addresses":[87],"them":[88],"separately.":[89],"first":[92],"step,":[93],"compiler":[94],"optimization":[95],"techniques":[96],"are":[97,108],"used":[98],"to":[99,110],"generate":[100],"suitable":[101],"data":[102],"flow":[103],"graphs.":[104,115],"Then":[105],"FPGA":[106],"configurations":[107],"assigned":[109],"these":[114],"Finally,":[116],"configuration":[118],"sequence":[119],"with":[120],"minimal":[122],"amount":[123],"reconfigurations":[125],"is":[126],"obtained":[127],"by":[128],"solving":[129],"Shortest-Common-Supersequence":[131],"problem.":[132]},"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}