{"id":"https://openalex.org/W1967506540","doi":"https://doi.org/10.1109/recosoc.2014.6861336","title":"A hardware/software co-design reconfigurable Network-on-Chip FPGA emulation method","display_name":"A hardware/software co-design reconfigurable Network-on-Chip FPGA emulation method","publication_year":2014,"publication_date":"2014-05-01","ids":{"openalex":"https://openalex.org/W1967506540","doi":"https://doi.org/10.1109/recosoc.2014.6861336","mag":"1967506540"},"language":"en","primary_location":{"id":"doi:10.1109/recosoc.2014.6861336","is_oa":false,"landing_page_url":"https://doi.org/10.1109/recosoc.2014.6861336","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5000716734","display_name":"Haoyuan Ying","orcid":null},"institutions":[{"id":"https://openalex.org/I31512782","display_name":"Technical University of Darmstadt","ror":"https://ror.org/05n911h24","country_code":"DE","type":"education","lineage":["https://openalex.org/I31512782"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Haoyuan Ying","raw_affiliation_strings":["Technische Universitat Darmstadt Fachbereich Biologie, Darmstadt, Hessen, DE","Integrated Electron. Syst. Lab., Tech. Univ. Darmstadt, Darmstadt, Germany"],"affiliations":[{"raw_affiliation_string":"Technische Universitat Darmstadt Fachbereich Biologie, Darmstadt, Hessen, DE","institution_ids":[]},{"raw_affiliation_string":"Integrated Electron. Syst. Lab., Tech. Univ. Darmstadt, Darmstadt, Germany","institution_ids":["https://openalex.org/I31512782"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5046831535","display_name":"Thomas Hollstein","orcid":"https://orcid.org/0000-0002-0454-6479"},"institutions":[{"id":"https://openalex.org/I111112146","display_name":"Tallinn University of Technology","ror":"https://ror.org/0443cwa12","country_code":"EE","type":"education","lineage":["https://openalex.org/I111112146"]}],"countries":["EE"],"is_corresponding":false,"raw_author_name":"Thomas Hollstein","raw_affiliation_strings":["Tallinna Tehnikaulikool, Tallinn, Harjumaa, EE","Tallinn University of Technology, Tallinn , Estonia"],"affiliations":[{"raw_affiliation_string":"Tallinna Tehnikaulikool, Tallinn, Harjumaa, EE","institution_ids":["https://openalex.org/I111112146"]},{"raw_affiliation_string":"Tallinn University of Technology, Tallinn , Estonia","institution_ids":["https://openalex.org/I111112146"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5061804977","display_name":"Klaus Hofmann","orcid":"https://orcid.org/0000-0002-6675-0221"},"institutions":[{"id":"https://openalex.org/I31512782","display_name":"Technical University of Darmstadt","ror":"https://ror.org/05n911h24","country_code":"DE","type":"education","lineage":["https://openalex.org/I31512782"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Klaus Hofmann","raw_affiliation_strings":["Technische Universitat Darmstadt Fachbereich Biologie, Darmstadt, Hessen, DE","Integrated Electron. Syst. Lab., Tech. Univ. Darmstadt, Darmstadt, Germany"],"affiliations":[{"raw_affiliation_string":"Technische Universitat Darmstadt Fachbereich Biologie, Darmstadt, Hessen, DE","institution_ids":[]},{"raw_affiliation_string":"Integrated Electron. Syst. Lab., Tech. Univ. Darmstadt, Darmstadt, Germany","institution_ids":["https://openalex.org/I31512782"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5000716734"],"corresponding_institution_ids":["https://openalex.org/I31512782"],"apc_list":null,"apc_paid":null,"fwci":1.3792,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.8245473,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"8"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/emulation","display_name":"Emulation","score":0.9347416162490845},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.767194390296936},{"id":"https://openalex.org/keywords/hardware-emulation","display_name":"Hardware emulation","score":0.7482578158378601},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7267324924468994},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7092124819755554},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.6683542728424072},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.6272314786911011},{"id":"https://openalex.org/keywords/network-on-a-chip","display_name":"Network on a chip","score":0.6254805326461792},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5398008823394775},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.5304094552993774},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4835790991783142},{"id":"https://openalex.org/keywords/fpga-prototype","display_name":"FPGA prototype","score":0.4455299973487854},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.11609438061714172}],"concepts":[{"id":"https://openalex.org/C149810388","wikidata":"https://www.wikidata.org/wiki/Q5374873","display_name":"Emulation","level":2,"score":0.9347416162490845},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.767194390296936},{"id":"https://openalex.org/C94115699","wikidata":"https://www.wikidata.org/wiki/Q5656406","display_name":"Hardware emulation","level":3,"score":0.7482578158378601},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7267324924468994},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7092124819755554},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.6683542728424072},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.6272314786911011},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.6254805326461792},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5398008823394775},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.5304094552993774},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4835790991783142},{"id":"https://openalex.org/C203864433","wikidata":"https://www.wikidata.org/wiki/Q5426992","display_name":"FPGA prototype","level":3,"score":0.4455299973487854},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.11609438061714172},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C50522688","wikidata":"https://www.wikidata.org/wiki/Q189833","display_name":"Economic growth","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/recosoc.2014.6861336","is_oa":false,"landing_page_url":"https://doi.org/10.1109/recosoc.2014.6861336","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)","raw_type":"proceedings-article"},{"id":"pmh:oai:tubiblio.ulb.tu-darmstadt.de:124873","is_oa":false,"landing_page_url":"http://tubiblio.ulb.tu-darmstadt.de/124873/","pdf_url":null,"source":{"id":"https://openalex.org/S4377196390","display_name":"TUbilio (Technical University of Darmstadt)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I31512782","host_organization_name":"Technische Universit\u00e4t Darmstadt","host_organization_lineage":["https://openalex.org/I31512782"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Konferenzver\u00f6ffentlichung"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.4099999964237213}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W35708471","https://openalex.org/W1958097946","https://openalex.org/W2015307980","https://openalex.org/W2018078084","https://openalex.org/W2048416686","https://openalex.org/W2076639234","https://openalex.org/W2103127274","https://openalex.org/W2104506252","https://openalex.org/W2108436158","https://openalex.org/W2118187287","https://openalex.org/W2135218079","https://openalex.org/W2147657366","https://openalex.org/W2544550464","https://openalex.org/W3151401188","https://openalex.org/W6679853584"],"related_works":["https://openalex.org/W2170071008","https://openalex.org/W2103996454","https://openalex.org/W2106791114","https://openalex.org/W3029775214","https://openalex.org/W2390650884","https://openalex.org/W2093057572","https://openalex.org/W2001552871","https://openalex.org/W119599369","https://openalex.org/W2888526229","https://openalex.org/W2122279357"],"abstract_inverted_index":{"Network-on-Chip":[0],"(NoC)":[1],"is":[2,28,62,78,90,135],"proposed":[3],"as":[4],"the":[5,17,68,75,87,95,110,116,121],"next":[6],"generation":[7],"interconnect":[8],"technique":[9],"for":[10,31,114],"multi/many":[11],"core":[12],"embedded":[13],"systems":[14],"due":[15],"to":[16,43,52,94],"high":[18],"performance":[19],"and":[20,24,35,47,65,112],"scalability.":[21],"An":[22],"efficient":[23,48],"correct":[25],"emulation":[26,88,101,125],"method":[27,51,61],"significantly":[29],"important":[30],"NoC":[32,54,70,97,117,131],"system":[33,55],"design":[34,56],"verification.":[36],"In":[37],"this":[38],"paper,":[39],"we":[40],"would":[41],"like":[42],"present":[44],"a":[45,127],"formalized":[46],"hardware/software":[49],"co-design":[50],"emulate":[53],"configurations":[57],"on":[58],"FPGA.":[59],"Our":[60],"reconfigurable,":[63],"flexible":[64],"platform-like.":[66],"Resynthesizing":[67],"hardware":[69,84,118],"platform":[71,89],"when":[72],"only":[73],"varying":[74],"target":[76],"applications":[77,105,134],"unnecessary":[79],"in":[80],"our":[81,100,124],"method.":[82],"The":[83],"part":[85],"of":[86,123,129],"generated":[91],"automatically":[92],"according":[93],"input":[96],"specifications":[98],"by":[99,109],"supporting":[102],"software.":[103],"Different":[104],"can":[106],"be":[107],"scheduled":[108],"software":[111],"utilized":[113],"emulating":[115,130],"design.":[119],"Besides":[120],"introduction":[122],"method,":[126],"demonstration":[128],"with":[132],"different":[133],"also":[136],"given.":[137]},"counts_by_year":[{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1}],"updated_date":"2026-02-26T08:16:20.718346","created_date":"2025-10-10T00:00:00"}