{"id":"https://openalex.org/W1967203441","doi":"https://doi.org/10.1109/recosoc.2013.6581547","title":"RecMIN: A reconfiguration architecture for network on chip","display_name":"RecMIN: A reconfiguration architecture for network on chip","publication_year":2013,"publication_date":"2013-07-01","ids":{"openalex":"https://openalex.org/W1967203441","doi":"https://doi.org/10.1109/recosoc.2013.6581547","mag":"1967203441"},"language":"en","primary_location":{"id":"doi:10.1109/recosoc.2013.6581547","is_oa":false,"landing_page_url":"https://doi.org/10.1109/recosoc.2013.6581547","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5019552160","display_name":"Alexander Logvinenko","orcid":null},"institutions":[{"id":"https://openalex.org/I167360494","display_name":"University of Wuppertal","ror":"https://ror.org/00613ak93","country_code":"DE","type":"education","lineage":["https://openalex.org/I167360494"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Alexander Logvinenko","raw_affiliation_strings":["University of Wuppertal, Wuppertal, Germany"],"affiliations":[{"raw_affiliation_string":"University of Wuppertal, Wuppertal, Germany","institution_ids":["https://openalex.org/I167360494"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5033106515","display_name":"Carsten Gremzow","orcid":null},"institutions":[{"id":"https://openalex.org/I167360494","display_name":"University of Wuppertal","ror":"https://ror.org/00613ak93","country_code":"DE","type":"education","lineage":["https://openalex.org/I167360494"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Carsten Gremzow","raw_affiliation_strings":["University of Wuppertal, Wuppertal, Germany"],"affiliations":[{"raw_affiliation_string":"University of Wuppertal, Wuppertal, Germany","institution_ids":["https://openalex.org/I167360494"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5000306618","display_name":"Dietmar Tutsch","orcid":"https://orcid.org/0009-0008-6495-5128"},"institutions":[{"id":"https://openalex.org/I167360494","display_name":"University of Wuppertal","ror":"https://ror.org/00613ak93","country_code":"DE","type":"education","lineage":["https://openalex.org/I167360494"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Dietmar Tutsch","raw_affiliation_strings":["University of Wuppertal, Wuppertal, Germany"],"affiliations":[{"raw_affiliation_string":"University of Wuppertal, Wuppertal, Germany","institution_ids":["https://openalex.org/I167360494"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5019552160"],"corresponding_institution_ids":["https://openalex.org/I167360494"],"apc_list":null,"apc_paid":null,"fwci":0.3625,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.62378679,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.996399998664856,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9939000010490417,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/control-reconfiguration","display_name":"Control reconfiguration","score":0.9173383712768555},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7269453406333923},{"id":"https://openalex.org/keywords/network-topology","display_name":"Network topology","score":0.6376827955245972},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6096574068069458},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.6033997535705566},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.5812982320785522},{"id":"https://openalex.org/keywords/logical-topology","display_name":"Logical topology","score":0.5524864196777344},{"id":"https://openalex.org/keywords/network-architecture","display_name":"Network architecture","score":0.5421960353851318},{"id":"https://openalex.org/keywords/network-on-a-chip","display_name":"Network on a chip","score":0.5213704705238342},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5174708962440491},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.4517006278038025},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.4457109570503235},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.4453333020210266},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.42965418100357056},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.424269437789917},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.14722943305969238},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.0855800211429596}],"concepts":[{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.9173383712768555},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7269453406333923},{"id":"https://openalex.org/C199845137","wikidata":"https://www.wikidata.org/wiki/Q145490","display_name":"Network topology","level":2,"score":0.6376827955245972},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6096574068069458},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.6033997535705566},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.5812982320785522},{"id":"https://openalex.org/C117729477","wikidata":"https://www.wikidata.org/wiki/Q145490","display_name":"Logical topology","level":3,"score":0.5524864196777344},{"id":"https://openalex.org/C193415008","wikidata":"https://www.wikidata.org/wiki/Q639681","display_name":"Network architecture","level":2,"score":0.5421960353851318},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.5213704705238342},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5174708962440491},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.4517006278038025},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.4457109570503235},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.4453333020210266},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.42965418100357056},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.424269437789917},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.14722943305969238},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0855800211429596},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/recosoc.2013.6581547","is_oa":false,"landing_page_url":"https://doi.org/10.1109/recosoc.2013.6581547","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W1521060328","https://openalex.org/W1531486443","https://openalex.org/W1592506883","https://openalex.org/W1976561704","https://openalex.org/W1985403683","https://openalex.org/W1989281572","https://openalex.org/W2129513217","https://openalex.org/W2134049183","https://openalex.org/W2143694280","https://openalex.org/W2144447762","https://openalex.org/W2147807513","https://openalex.org/W2165670411","https://openalex.org/W2294425876","https://openalex.org/W4234308027","https://openalex.org/W4235219143","https://openalex.org/W4252808968","https://openalex.org/W4285719527","https://openalex.org/W6635480731"],"related_works":["https://openalex.org/W2357657342","https://openalex.org/W2153432761","https://openalex.org/W1580144672","https://openalex.org/W2152623100","https://openalex.org/W2142042635","https://openalex.org/W2360310172","https://openalex.org/W3170183406","https://openalex.org/W4253943116","https://openalex.org/W2027234836","https://openalex.org/W2050961419"],"abstract_inverted_index":{"RecMIN":[0,33],"(Reconfigurable":[1],"Multi-Interconnection":[2],"Network)":[3],"is":[4,59],"a":[5],"new":[6],"network":[7,22,74,79],"architecture":[8,62],"that":[9],"reduces":[10],"inefficiency":[11],"and":[12,53,81],"increases":[13],"the":[14,17,21,31,54,86,89],"throughput":[15],"of":[16,36,42,56,78,88],"network.":[18],"With":[19],"reconfiguration,":[20],"topology":[23,34],"adapts":[24],"itself":[25],"to":[26,67],"traffic.":[27],"Like":[28],"FPGA":[29],"topology,":[30],"proposed":[32],"consists":[35],"dynamically":[37],"reconfigurable":[38,69],"cells.":[39],"The":[40,61,76],"reconfiguration":[41,55],"each":[43,57],"cell":[44,58],"can":[45,63],"possibly":[46],"be":[47,64],"done":[48],"in":[49],"one":[50],"clock":[51],"cycle,":[52],"independent.":[60],"easily":[65],"expanded":[66],"utilize":[68],"cells":[70],"together":[71],"with":[72],"non-reconfigurable":[73],"structures.":[75],"number":[77],"inputs":[80],"outputs":[82],"does":[83],"not":[84],"affect":[85],"viability":[87],"architecture.":[90]},"counts_by_year":[{"year":2016,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}