{"id":"https://openalex.org/W2095925635","doi":"https://doi.org/10.1109/recosoc.2013.6581537","title":"Memory allocation and optimization in system-level architectural synthesis","display_name":"Memory allocation and optimization in system-level architectural synthesis","publication_year":2013,"publication_date":"2013-07-01","ids":{"openalex":"https://openalex.org/W2095925635","doi":"https://doi.org/10.1109/recosoc.2013.6581537","mag":"2095925635"},"language":"en","primary_location":{"id":"doi:10.1109/recosoc.2013.6581537","is_oa":false,"landing_page_url":"https://doi.org/10.1109/recosoc.2013.6581537","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100386630","display_name":"Shuo Li","orcid":"https://orcid.org/0000-0002-5184-3230"},"institutions":[{"id":"https://openalex.org/I86987016","display_name":"KTH Royal Institute of Technology","ror":"https://ror.org/026vcq606","country_code":"SE","type":"education","lineage":["https://openalex.org/I86987016"]}],"countries":["SE"],"is_corresponding":false,"raw_author_name":"Shuo Li","raw_affiliation_strings":["Department of Electronic Systems, School of Information and Communication Technology, Royal Institute of Technology, Stockholm, Sweden","Dept. of Electron. Syst., R. Inst. of Technol., Stockholm, Sweden"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronic Systems, School of Information and Communication Technology, Royal Institute of Technology, Stockholm, Sweden","institution_ids":["https://openalex.org/I86987016"]},{"raw_affiliation_string":"Dept. of Electron. Syst., R. Inst. of Technol., Stockholm, Sweden","institution_ids":["https://openalex.org/I86987016"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5026355063","display_name":"Ahmed Hemani","orcid":"https://orcid.org/0000-0003-0565-9376"},"institutions":[{"id":"https://openalex.org/I86987016","display_name":"KTH Royal Institute of Technology","ror":"https://ror.org/026vcq606","country_code":"SE","type":"education","lineage":["https://openalex.org/I86987016"]}],"countries":["SE"],"is_corresponding":false,"raw_author_name":"Ahmed Hemani","raw_affiliation_strings":["Department of Electronic Systems, School of Information and Communication Technology, Royal Institute of Technology, Stockholm, Sweden","Dept. of Electron. Syst., R. Inst. of Technol., Stockholm, Sweden"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronic Systems, School of Information and Communication Technology, Royal Institute of Technology, Stockholm, Sweden","institution_ids":["https://openalex.org/I86987016"]},{"raw_affiliation_string":"Dept. of Electron. Syst., R. Inst. of Technol., Stockholm, Sweden","institution_ids":["https://openalex.org/I86987016"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I86987016"],"apc_list":null,"apc_paid":null,"fwci":0.538,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.61113344,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"7"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.825285792350769},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.7781684994697571},{"id":"https://openalex.org/keywords/dataflow","display_name":"Dataflow","score":0.5536167621612549},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5535797476768494},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5400235652923584},{"id":"https://openalex.org/keywords/resource-allocation","display_name":"Resource allocation","score":0.525009274482727},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.5178042650222778},{"id":"https://openalex.org/keywords/flat-memory-model","display_name":"Flat memory model","score":0.5103310942649841},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4741194546222687},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.4444507956504822},{"id":"https://openalex.org/keywords/register-allocation","display_name":"Register allocation","score":0.4269603490829468},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.42021384835243225},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.41997572779655457},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.4197336733341217},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.27040213346481323},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.2355518341064453},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.208279550075531},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.13208723068237305}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.825285792350769},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.7781684994697571},{"id":"https://openalex.org/C96324660","wikidata":"https://www.wikidata.org/wiki/Q205446","display_name":"Dataflow","level":2,"score":0.5536167621612549},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5535797476768494},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5400235652923584},{"id":"https://openalex.org/C29202148","wikidata":"https://www.wikidata.org/wiki/Q287260","display_name":"Resource allocation","level":2,"score":0.525009274482727},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.5178042650222778},{"id":"https://openalex.org/C57863822","wikidata":"https://www.wikidata.org/wiki/Q905488","display_name":"Flat memory model","level":4,"score":0.5103310942649841},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4741194546222687},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.4444507956504822},{"id":"https://openalex.org/C128916667","wikidata":"https://www.wikidata.org/wiki/Q1343660","display_name":"Register allocation","level":3,"score":0.4269603490829468},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.42021384835243225},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.41997572779655457},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.4197336733341217},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.27040213346481323},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.2355518341064453},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.208279550075531},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.13208723068237305},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/recosoc.2013.6581537","is_oa":false,"landing_page_url":"https://doi.org/10.1109/recosoc.2013.6581537","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":22,"referenced_works":["https://openalex.org/W1872025194","https://openalex.org/W1965359258","https://openalex.org/W2012046244","https://openalex.org/W2027678333","https://openalex.org/W2033933061","https://openalex.org/W2046679083","https://openalex.org/W2077572333","https://openalex.org/W2091158003","https://openalex.org/W2103792548","https://openalex.org/W2110860124","https://openalex.org/W2112678088","https://openalex.org/W2122546367","https://openalex.org/W2133737198","https://openalex.org/W2138305065","https://openalex.org/W2147200311","https://openalex.org/W2169180789","https://openalex.org/W3146054601","https://openalex.org/W4235344346","https://openalex.org/W4247461773","https://openalex.org/W6638998102","https://openalex.org/W6660295455","https://openalex.org/W6662051672"],"related_works":["https://openalex.org/W2461217932","https://openalex.org/W3206653210","https://openalex.org/W2134941280","https://openalex.org/W2172010869","https://openalex.org/W2122030400","https://openalex.org/W2352470693","https://openalex.org/W2145993717","https://openalex.org/W2269990635","https://openalex.org/W2543290882","https://openalex.org/W2295153704"],"abstract_inverted_index":{"In":[0],"this":[1,90],"paper,":[2],"we":[3],"present":[4],"a":[5,14,20,59,98,113],"novel":[6],"approach":[7],"to":[8,64,78,189],"optimally":[9,79,120],"allocate":[10,80],"memory":[11,75,81,100,104,114,136,144,196],"resources":[12,82,187],"in":[13,33,83,106,124],"system-level":[15],"synthesis":[16,49],"flow,":[17],"which":[18,95],"converts":[19],"dataflow":[21],"style":[22,37,150],"system":[23,210],"description":[24,32],"(synchronous":[25],"data":[26],"flow)":[27],"into":[28],"the":[29,34,48,74,84,125,171,209],"register-transfer":[30],"level":[31],"specified":[35],"implementation":[36,57,149,181],"(ASIC,":[38],"FPGA":[39,108],"or":[40],"CGRA).":[41],"The":[42,70,87,143,166,178,192],"first":[43],"problem":[44,72],"is":[45,51,62,73,147,174],"encountered":[46],"by":[47],"flow":[50],"that":[52,170,204],"since":[53],"it":[54],"covers":[55],"different":[56,103],"styles,":[58],"generic":[60,99],"model":[61,101],"required":[63],"support":[65],"resource":[66,160],"allocation":[67,76,115,145,161,197],"and":[68,109,111,116,138,153,162,176,194],"optimization.":[69,165],"second":[71],"method":[77,118,146,173,198],"RTL":[85],"model.":[86],"contribution":[88],"of":[89],"paper":[91],"has":[92,154],"two":[93],"parts,":[94],"are":[96],"1)":[97],"for":[102,119,134,141],"architectures":[105],"ASIC,":[107,135],"CGRA,":[110],"2)":[112],"optimization":[117],"allocating":[121],"storage":[122],"elements":[123],"intermediate":[126],"representation":[127],"with":[128],"actual":[129],"implementations":[130],"(e.g.":[131],"on-chip":[132],"SRAM":[133],"controller":[137],"off-chip":[139],"SDRAM":[140],"FPGA).":[142],"an":[148],"dependent":[151],"procedure":[152],"three":[155],"steps:":[156],"architecture":[157,163],"independent":[158],"optimization,":[159],"depended":[164],"experimental":[167],"result":[168],"shows":[169],"proposed":[172],"efficient":[175],"effective.":[177],"automatically":[179],"generated":[180],"uses":[182],"only":[183],"approximately":[184],"4%":[185],"more":[186],"compared":[188],"manual":[190],"implementation.":[191],"fast":[193,200],"automatic":[195],"enables":[199],"design":[201],"space":[202],"exploration":[203],"requires":[205],"little":[206],"effort":[207],"form":[208],"designer.":[211]},"counts_by_year":[{"year":2016,"cited_by_count":1},{"year":2014,"cited_by_count":2}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
