{"id":"https://openalex.org/W2113104980","doi":"https://doi.org/10.1109/recosoc.2013.6581525","title":"Measuring memory access latency for software objects in a NUMA system-on-chip architecture","display_name":"Measuring memory access latency for software objects in a NUMA system-on-chip architecture","publication_year":2013,"publication_date":"2013-07-01","ids":{"openalex":"https://openalex.org/W2113104980","doi":"https://doi.org/10.1109/recosoc.2013.6581525","mag":"2113104980"},"language":"en","primary_location":{"id":"doi:10.1109/recosoc.2013.6581525","is_oa":false,"landing_page_url":"https://doi.org/10.1109/recosoc.2013.6581525","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)","raw_type":"proceedings-article"},"type":"preprint","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5030174987","display_name":"Daniela Genius","orcid":"https://orcid.org/0000-0002-9410-6716"},"institutions":[{"id":"https://openalex.org/I39804081","display_name":"Sorbonne Universit\u00e9","ror":"https://ror.org/02en5vm52","country_code":"FR","type":"education","lineage":["https://openalex.org/I39804081"]}],"countries":["FR"],"is_corresponding":true,"raw_author_name":"Daniela Genius","raw_affiliation_strings":["LIP6, Universit\u00e9 Pierre et Marie Curie, Paris, France","Univ. Pierre et Marie Curie, Paris, France"],"affiliations":[{"raw_affiliation_string":"LIP6, Universit\u00e9 Pierre et Marie Curie, Paris, France","institution_ids":["https://openalex.org/I39804081"]},{"raw_affiliation_string":"Univ. Pierre et Marie Curie, Paris, France","institution_ids":["https://openalex.org/I39804081"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5030174987"],"corresponding_institution_ids":["https://openalex.org/I39804081"],"apc_list":null,"apc_paid":null,"fwci":1.2933,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.81750871,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"8"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8378223180770874},{"id":"https://openalex.org/keywords/mpsoc","display_name":"MPSoC","score":0.7390393018722534},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.47408878803253174},{"id":"https://openalex.org/keywords/uniform-memory-access","display_name":"Uniform memory access","score":0.47181782126426697},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.46718791127204895},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.45689013600349426},{"id":"https://openalex.org/keywords/memory-map","display_name":"Memory map","score":0.45161110162734985},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.44650697708129883},{"id":"https://openalex.org/keywords/registered-memory","display_name":"Registered memory","score":0.44398248195648193},{"id":"https://openalex.org/keywords/shared-memory","display_name":"Shared memory","score":0.4394555687904358},{"id":"https://openalex.org/keywords/network-packet","display_name":"Network packet","score":0.41619592905044556},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.3624778389930725},{"id":"https://openalex.org/keywords/overlay","display_name":"Overlay","score":0.3292059600353241},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.30567246675491333},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2785685360431671},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.2327885925769806},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.1827976405620575}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8378223180770874},{"id":"https://openalex.org/C2777187653","wikidata":"https://www.wikidata.org/wiki/Q975106","display_name":"MPSoC","level":3,"score":0.7390393018722534},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.47408878803253174},{"id":"https://openalex.org/C51290061","wikidata":"https://www.wikidata.org/wiki/Q1936765","display_name":"Uniform memory access","level":4,"score":0.47181782126426697},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.46718791127204895},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.45689013600349426},{"id":"https://openalex.org/C74426580","wikidata":"https://www.wikidata.org/wiki/Q719484","display_name":"Memory map","level":3,"score":0.45161110162734985},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.44650697708129883},{"id":"https://openalex.org/C93446704","wikidata":"https://www.wikidata.org/wiki/Q449328","display_name":"Registered memory","level":3,"score":0.44398248195648193},{"id":"https://openalex.org/C133875982","wikidata":"https://www.wikidata.org/wiki/Q764810","display_name":"Shared memory","level":2,"score":0.4394555687904358},{"id":"https://openalex.org/C158379750","wikidata":"https://www.wikidata.org/wiki/Q214111","display_name":"Network packet","level":2,"score":0.41619592905044556},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.3624778389930725},{"id":"https://openalex.org/C136085584","wikidata":"https://www.wikidata.org/wiki/Q910289","display_name":"Overlay","level":2,"score":0.3292059600353241},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.30567246675491333},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2785685360431671},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.2327885925769806},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.1827976405620575},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/recosoc.2013.6581525","is_oa":false,"landing_page_url":"https://doi.org/10.1109/recosoc.2013.6581525","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)","raw_type":"proceedings-article"},{"id":"pmh:oai:HAL:hal-01216503v1","is_oa":false,"landing_page_url":"https://hal.science/hal-01216503","pdf_url":null,"source":{"id":"https://openalex.org/S4306402512","display_name":"HAL (Le Centre pour la Communication Scientifique Directe)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1294671590","host_organization_name":"Centre National de la Recherche Scientifique","host_organization_lineage":["https://openalex.org/I1294671590"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip, ReCoSoC 2013, Jul 2013, Darmstadt, Germany. pp.1-8, &#x27E8;10.1109/ReCoSoC.2013.6581525&#x27E9;","raw_type":"Conference papers"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W170298805","https://openalex.org/W228202226","https://openalex.org/W1597755753","https://openalex.org/W2061537881","https://openalex.org/W2096287216","https://openalex.org/W2096835686","https://openalex.org/W2121562991","https://openalex.org/W2125508346","https://openalex.org/W2130484824","https://openalex.org/W2153484975","https://openalex.org/W2156858199","https://openalex.org/W2168681242","https://openalex.org/W2959127858","https://openalex.org/W4229941096","https://openalex.org/W4239035626","https://openalex.org/W4248559451","https://openalex.org/W6609095524","https://openalex.org/W6635964534","https://openalex.org/W6677927856","https://openalex.org/W6765485035"],"related_works":["https://openalex.org/W4232365528","https://openalex.org/W3021597805","https://openalex.org/W2041174925","https://openalex.org/W2296275612","https://openalex.org/W4248614727","https://openalex.org/W2612506697","https://openalex.org/W2354036839","https://openalex.org/W254684032","https://openalex.org/W4233816696","https://openalex.org/W43633106"],"abstract_inverted_index":{"We":[0,147,170],"consider":[1],"streaming":[2],"applications":[3,33],"modeled":[4,95],"as":[5],"a":[6,21,140,143],"set":[7],"of":[8,20,44,67,116,118,185,192],"tasks":[9],"communicating":[10],"via":[11,54],"channels.":[12,50],"These":[13],"channels":[14,107],"are":[15,123],"mapped":[16,124],"to":[17,77,86,125,134,166],"on-chip":[18,126],"memory":[19,29,110,181],"multi-processor":[22],"system":[23],"on":[24,69,72,158],"chip":[25],"(MPSoC)":[26],"with":[27,96],"non-uniform":[28],"access.":[30],"In":[31,183],"complex":[32],"like":[34,59],"advanced":[35],"packet":[36],"processing":[37],"and":[38,61,87,108,177,199],"video":[39],"streaming,":[40],"often":[41],"only":[42],"part":[43],"the":[45,49,70,73,151,156,159,164,172,179,186,202],"data":[46],"transits":[47],"through":[48],"Tasks":[51],"also":[52,75],"communicate":[53],"shared":[55,109],"memory;":[56],"synchronization":[57],"mechanisms":[58],"locks":[60],"barriers":[62],"might":[63],"be":[64,78],"required.":[65],"Effects":[66],"I/O":[68],"traffic":[71,85],"interconnect":[74],"have":[76],"taken":[79],"into":[80],"account,":[81],"all":[82],"together":[83],"increasing":[84],"from":[88],"memory.":[89,127],"Our":[90],"clustered":[91],"MPSoC":[92],"architecture":[93],"is":[94,133],"SoCLib.":[97],"SocLib's":[98],"design":[99,152],"space":[100],"exploration":[101],"tool":[102],"proposes,":[103],"among":[104],"others,":[105],"communication":[106],"for":[111,142],"inter-task":[112],"communication.":[113],"Each":[114],"consists":[115],"one":[117],"several":[119],"software":[120,145,168,173],"objects":[121,174],"which":[122,137],"The":[128],"difficulty":[129],"when":[130],"measuring":[131],"latency":[132],"find":[135],"out":[136],"(co-)processor":[138],"issued":[139],"request":[141],"particular":[144],"object.":[146],"intervene":[148],"early":[149],"in":[150],"process":[153],"by":[154,163,175],"monitoring":[155],"transfers":[157],"interconnection":[160],"network":[161],"caused":[162],"access":[165],"these":[167],"objects.":[169],"identify":[171],"name":[176],"trace":[178],"corresponding":[180],"accesses.":[182],"spite":[184],"cycle":[187],"accurate":[188,190],"bit":[189],"level":[191],"simulation,":[193],"our":[194],"method":[195],"has":[196],"little":[197],"overhead":[198],"avoids":[200],"distorting":[201],"performance":[203],"results.":[204]},"counts_by_year":[{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1}],"updated_date":"2026-03-10T16:38:18.471706","created_date":"2025-10-10T00:00:00"}
