{"id":"https://openalex.org/W2042363329","doi":"https://doi.org/10.1109/recosoc.2013.6581522","title":"Register allocation for high-level synthesis of hardware accelerators targeting FPGAs","display_name":"Register allocation for high-level synthesis of hardware accelerators targeting FPGAs","publication_year":2013,"publication_date":"2013-07-01","ids":{"openalex":"https://openalex.org/W2042363329","doi":"https://doi.org/10.1109/recosoc.2013.6581522","mag":"2042363329"},"language":"en","primary_location":{"id":"doi:10.1109/recosoc.2013.6581522","is_oa":false,"landing_page_url":"https://doi.org/10.1109/recosoc.2013.6581522","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5046466505","display_name":"Gerald Hempel","orcid":"https://orcid.org/0000-0002-4737-8612"},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"TU Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Gerald Hempel","raw_affiliation_strings":["Chair for Embedded Systems, Technische Universit\u00e4t Dresden, Dresden, Germany","Embedded Syst., Tech. Univ. Dresden, Dresden, Germany"],"affiliations":[{"raw_affiliation_string":"Chair for Embedded Systems, Technische Universit\u00e4t Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]},{"raw_affiliation_string":"Embedded Syst., Tech. Univ. Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5047852089","display_name":"Jan Hoyer","orcid":null},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"TU Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Jan Hoyer","raw_affiliation_strings":["Chair for Embedded Systems, Technische Universit\u00e4t Dresden, Dresden, Germany","Embedded Syst., Tech. Univ. Dresden, Dresden, Germany"],"affiliations":[{"raw_affiliation_string":"Chair for Embedded Systems, Technische Universit\u00e4t Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]},{"raw_affiliation_string":"Embedded Syst., Tech. Univ. Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5080637249","display_name":"Thilo Pionteck","orcid":"https://orcid.org/0000-0001-6518-1226"},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"TU Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Thilo Pionteck","raw_affiliation_strings":["Chair for Embedded Systems, Technische Universit\u00e4t Dresden, Dresden, Germany","Embedded Syst., Tech. Univ. Dresden, Dresden, Germany"],"affiliations":[{"raw_affiliation_string":"Chair for Embedded Systems, Technische Universit\u00e4t Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]},{"raw_affiliation_string":"Embedded Syst., Tech. Univ. Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5005076278","display_name":"Christian Hochberger","orcid":"https://orcid.org/0000-0001-5516-7826"},"institutions":[{"id":"https://openalex.org/I31512782","display_name":"Technical University of Darmstadt","ror":"https://ror.org/05n911h24","country_code":"DE","type":"education","lineage":["https://openalex.org/I31512782"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Christian Hochberger","raw_affiliation_strings":["Computer Systems Group, Technische Universit\u00e4t Darmstadt, Darmstadt, Germany","Comput. Syst. Group, Tech. Univ. Darmstadt, Darmstadt, Germany"],"affiliations":[{"raw_affiliation_string":"Computer Systems Group, Technische Universit\u00e4t Darmstadt, Darmstadt, Germany","institution_ids":["https://openalex.org/I31512782"]},{"raw_affiliation_string":"Comput. Syst. Group, Tech. Univ. Darmstadt, Darmstadt, Germany","institution_ids":["https://openalex.org/I31512782"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5046466505"],"corresponding_institution_ids":["https://openalex.org/I78650965"],"apc_list":null,"apc_paid":null,"fwci":0.3152,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.60191054,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8344277143478394},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7290776968002319},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.7232042551040649},{"id":"https://openalex.org/keywords/register-allocation","display_name":"Register allocation","score":0.6311848163604736},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5851402878761292},{"id":"https://openalex.org/keywords/vendor","display_name":"Vendor","score":0.5636629462242126},{"id":"https://openalex.org/keywords/context","display_name":"Context (archaeology)","score":0.5498858690261841},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.5238447189331055},{"id":"https://openalex.org/keywords/suite","display_name":"Suite","score":0.49157294631004333},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3885493874549866},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.38639822602272034},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.18986102938652039}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8344277143478394},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7290776968002319},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.7232042551040649},{"id":"https://openalex.org/C128916667","wikidata":"https://www.wikidata.org/wiki/Q1343660","display_name":"Register allocation","level":3,"score":0.6311848163604736},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5851402878761292},{"id":"https://openalex.org/C2777338717","wikidata":"https://www.wikidata.org/wiki/Q1762621","display_name":"Vendor","level":2,"score":0.5636629462242126},{"id":"https://openalex.org/C2779343474","wikidata":"https://www.wikidata.org/wiki/Q3109175","display_name":"Context (archaeology)","level":2,"score":0.5498858690261841},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.5238447189331055},{"id":"https://openalex.org/C79581498","wikidata":"https://www.wikidata.org/wiki/Q1367530","display_name":"Suite","level":2,"score":0.49157294631004333},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3885493874549866},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.38639822602272034},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.18986102938652039},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.0},{"id":"https://openalex.org/C166957645","wikidata":"https://www.wikidata.org/wiki/Q23498","display_name":"Archaeology","level":1,"score":0.0},{"id":"https://openalex.org/C95457728","wikidata":"https://www.wikidata.org/wiki/Q309","display_name":"History","level":0,"score":0.0},{"id":"https://openalex.org/C162853370","wikidata":"https://www.wikidata.org/wiki/Q39809","display_name":"Marketing","level":1,"score":0.0},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C144133560","wikidata":"https://www.wikidata.org/wiki/Q4830453","display_name":"Business","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/recosoc.2013.6581522","is_oa":false,"landing_page_url":"https://doi.org/10.1109/recosoc.2013.6581522","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320328735","display_name":"Freistaat Sachsen","ror":null},{"id":"https://openalex.org/F4320338080","display_name":"European Social Fund","ror":"https://ror.org/00k4n6c32"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1989240008","https://openalex.org/W2018055497","https://openalex.org/W2041815857","https://openalex.org/W2071166234","https://openalex.org/W2114266730","https://openalex.org/W2124432497","https://openalex.org/W2127699991","https://openalex.org/W2145947338","https://openalex.org/W2151310824","https://openalex.org/W2161707787","https://openalex.org/W2188922879","https://openalex.org/W4232601010","https://openalex.org/W6687424872"],"related_works":["https://openalex.org/W2172010869","https://openalex.org/W2122030400","https://openalex.org/W2145993717","https://openalex.org/W2352470693","https://openalex.org/W2269990635","https://openalex.org/W2543290882","https://openalex.org/W2295153704","https://openalex.org/W2010813303","https://openalex.org/W4367591616","https://openalex.org/W1490270176"],"abstract_inverted_index":{"This":[0],"work":[1],"evaluates":[2],"the":[3,44,72,108],"benefits":[4],"of":[5,12,19,27,74,92],"several":[6,65,93],"register":[7,66,140],"allocation":[8,67,141],"strategies":[9,68],"as":[10,62,117,151],"part":[11],"a":[13,75],"design":[14,29,51,81,110,157],"flow":[15,82],"for":[16,33,43,83,100,123,154],"automatic":[17],"generation":[18],"application-specific":[20,84],"hardware":[21,56,85],"accelerators":[22],"targeting":[23,36],"FPGAs.":[24],"As":[25],"usage":[26],"vendor-specific":[28,156],"tools":[30],"is":[31],"mandatory":[32],"system":[34],"designs":[35,95,104],"FPGAs,":[37],"high-level":[38],"synthesis":[39],"has":[40],"to":[41,59,79,134],"account":[42],"optimization":[45,119],"capabilities":[46],"already":[47],"implemented":[48],"in":[49,71],"these":[50],"tools.":[52,158],"In":[53],"addition,":[54],"FPGA-specific":[55],"characteristics":[57],"have":[58],"be":[60,144],"considered":[61],"well.":[63],"Therefore,":[64],"are":[69],"evaluated":[70],"context":[73],"GCC":[76],"based":[77],"C":[78],"HDL":[80,149],"accelerators.":[86],"Evaluation":[87],"was":[88],"done":[89],"by":[90],"means":[91],"example":[94],"from":[96],"typical":[97],"application":[98],"domains":[99],"embedded":[101],"systems.":[102],"These":[103],"were":[105],"synthesized":[106],"using":[107],"ISE":[109],"suite":[111],"with":[112,132],"either":[113],"area":[114,138],"or":[115],"speed":[116],"an":[118,152],"criteria.":[120],"Synthesis":[121],"results":[122],"Spartan":[124],"6":[125],"and":[126,137],"Artix":[127],"7":[128],"FPGAs":[129],"show":[130],"that":[131],"regards":[133],"clock":[135],"frequency":[136],"requirements,":[139],"strategy":[142],"should":[143],"kept":[145],"simple":[146],"when":[147],"generating":[148],"code":[150],"input":[153],"FPGA":[155]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2015,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
