{"id":"https://openalex.org/W1981726186","doi":"https://doi.org/10.1109/recosoc.2013.6581521","title":"SoC performance evaluation with ArchC and TLM-2.0","display_name":"SoC performance evaluation with ArchC and TLM-2.0","publication_year":2013,"publication_date":"2013-07-01","ids":{"openalex":"https://openalex.org/W1981726186","doi":"https://doi.org/10.1109/recosoc.2013.6581521","mag":"1981726186"},"language":"en","primary_location":{"id":"doi:10.1109/recosoc.2013.6581521","is_oa":false,"landing_page_url":"https://doi.org/10.1109/recosoc.2013.6581521","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5112526412","display_name":"J\u00f6rg Walter","orcid":null},"institutions":[{"id":"https://openalex.org/I202367325","display_name":"Oldenburger Institut f\u00fcr Informatik","ror":"https://ror.org/003sav189","country_code":"DE","type":"facility","lineage":["https://openalex.org/I202367325"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Jorg Walter","raw_affiliation_strings":["OFFIS Institute for Information Technology, Oldenburg, Germany","OFFIS\u2014Institute for Information Technology, Oldenburg, Germany"],"affiliations":[{"raw_affiliation_string":"OFFIS Institute for Information Technology, Oldenburg, Germany","institution_ids":["https://openalex.org/I202367325"]},{"raw_affiliation_string":"OFFIS\u2014Institute for Information Technology, Oldenburg, Germany","institution_ids":["https://openalex.org/I202367325"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5055024807","display_name":"J\u00f6rg Lenhardt","orcid":null},"institutions":[{"id":"https://openalex.org/I120691247","display_name":"University of Hagen","ror":"https://ror.org/04tkkr536","country_code":"DE","type":"education","lineage":["https://openalex.org/I120691247"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Jorg Lenhardt","raw_affiliation_strings":["Faculty of Mathematics and Computer Science Computer Architecture Group, University of Hagen, Germany","Fac. of Math. & Comput. Sci., Univ. of Hagen, Hagen, Germany"],"affiliations":[{"raw_affiliation_string":"Faculty of Mathematics and Computer Science Computer Architecture Group, University of Hagen, Germany","institution_ids":["https://openalex.org/I120691247"]},{"raw_affiliation_string":"Fac. of Math. & Comput. Sci., Univ. of Hagen, Hagen, Germany","institution_ids":["https://openalex.org/I120691247"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5053996949","display_name":"Wolfram Schiffmann","orcid":null},"institutions":[{"id":"https://openalex.org/I120691247","display_name":"University of Hagen","ror":"https://ror.org/04tkkr536","country_code":"DE","type":"education","lineage":["https://openalex.org/I120691247"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Wolfram Schiffmann","raw_affiliation_strings":["Faculty of Mathematics and Computer Science Computer Architecture Group, University of Hagen, Germany","Fac. of Math. & Comput. Sci., Univ. of Hagen, Hagen, Germany"],"affiliations":[{"raw_affiliation_string":"Faculty of Mathematics and Computer Science Computer Architecture Group, University of Hagen, Germany","institution_ids":["https://openalex.org/I120691247"]},{"raw_affiliation_string":"Fac. of Math. & Comput. Sci., Univ. of Hagen, Hagen, Germany","institution_ids":["https://openalex.org/I120691247"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5112526412"],"corresponding_institution_ids":["https://openalex.org/I202367325"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.06222659,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"152","issue":null,"first_page":"1","last_page":"8"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/systemc","display_name":"SystemC","score":0.9762004017829895},{"id":"https://openalex.org/keywords/transaction-level-modeling","display_name":"Transaction-level modeling","score":0.8901256918907166},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8468632698059082},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.597673237323761},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.526127815246582},{"id":"https://openalex.org/keywords/workload","display_name":"Workload","score":0.5201683044433594},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.517876386642456},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.5109123587608337},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.5033666491508484},{"id":"https://openalex.org/keywords/electronic-system-level-design-and-verification","display_name":"Electronic system-level design and verification","score":0.47600945830345154},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.4756029546260834},{"id":"https://openalex.org/keywords/upgrade","display_name":"Upgrade","score":0.4705405831336975},{"id":"https://openalex.org/keywords/database-transaction","display_name":"Database transaction","score":0.45597729086875916},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3048650324344635},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.2956245541572571},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.22537964582443237}],"concepts":[{"id":"https://openalex.org/C2776928060","wikidata":"https://www.wikidata.org/wiki/Q1753563","display_name":"SystemC","level":2,"score":0.9762004017829895},{"id":"https://openalex.org/C169571997","wikidata":"https://www.wikidata.org/wiki/Q966099","display_name":"Transaction-level modeling","level":3,"score":0.8901256918907166},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8468632698059082},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.597673237323761},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.526127815246582},{"id":"https://openalex.org/C2778476105","wikidata":"https://www.wikidata.org/wiki/Q628539","display_name":"Workload","level":2,"score":0.5201683044433594},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.517876386642456},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.5109123587608337},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.5033666491508484},{"id":"https://openalex.org/C77495112","wikidata":"https://www.wikidata.org/wiki/Q5358436","display_name":"Electronic system-level design and verification","level":2,"score":0.47600945830345154},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.4756029546260834},{"id":"https://openalex.org/C2780615140","wikidata":"https://www.wikidata.org/wiki/Q920419","display_name":"Upgrade","level":2,"score":0.4705405831336975},{"id":"https://openalex.org/C75949130","wikidata":"https://www.wikidata.org/wiki/Q848010","display_name":"Database transaction","level":2,"score":0.45597729086875916},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3048650324344635},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.2956245541572571},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.22537964582443237},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/recosoc.2013.6581521","is_oa":false,"landing_page_url":"https://doi.org/10.1109/recosoc.2013.6581521","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W141583583","https://openalex.org/W154106227","https://openalex.org/W1594347742","https://openalex.org/W1686420892","https://openalex.org/W1967441349","https://openalex.org/W1998849536","https://openalex.org/W2134855419","https://openalex.org/W2151415616","https://openalex.org/W2542693654","https://openalex.org/W4232544325","https://openalex.org/W4234101161","https://openalex.org/W4244854666","https://openalex.org/W4244878519","https://openalex.org/W6605794956","https://openalex.org/W6606274320","https://openalex.org/W6635941905","https://openalex.org/W6637151178"],"related_works":["https://openalex.org/W1525398417","https://openalex.org/W2532163536","https://openalex.org/W2266880325","https://openalex.org/W2069603759","https://openalex.org/W2533881872","https://openalex.org/W2149449165","https://openalex.org/W2119788505","https://openalex.org/W1576344679","https://openalex.org/W2059569687","https://openalex.org/W4238487776"],"abstract_inverted_index":{"ArchC":[0,42,66],"is":[1,18],"an":[2,39,65,97],"architecture":[3,100],"description":[4],"language":[5],"that":[6,43],"provides":[7],"instruction":[8],"set":[9],"level":[10,31],"simulation":[11,90,94],"and":[12,22,47,91],"binary":[13],"tool":[14],"chain":[15],"generation.":[16],"It":[17],"based":[19],"on":[20],"SystemC":[21,27],"can":[23,83],"communicate":[24],"with":[25],"other":[26],"components":[28],"using":[29],"transaction":[30],"modeling":[32],"(TLM).":[33],"In":[34],"this":[35],"article":[36],"we":[37,72],"present":[38],"upgrade":[40],"of":[41,59,87],"allows":[44],"TLM-2.0":[45],"usage":[46],"makes":[48],"it":[49],"available":[50],"in":[51],"timed":[52,93],"simulations.":[53],"These":[54],"extensions":[55],"enable":[56],"performance":[57],"evaluation":[58],"complete":[60],"System-on-Chip":[61],"designs":[62],"built":[63],"around":[64],"processor":[67],"model.":[68],"As":[69],"a":[70,85,102],"proof-of-concept,":[71],"examine":[73],"various":[74],"TLM-connected":[75],"memory":[76],"hierarchies.":[77],"We":[78],"outline":[79],"how":[80],"model":[81],"designers":[82],"use":[84],"combination":[86],"fast":[88],"functional":[89],"slow":[92],"to":[95],"determine":[96],"optimal":[98],"system":[99],"for":[101],"given":[103],"workload.":[104]},"counts_by_year":[{"year":2018,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
