{"id":"https://openalex.org/W3006305014","doi":"https://doi.org/10.1109/reconfig48160.2019.8994796","title":"A Catalog and In-Hardware Evaluation of Open-Source Drop-In Compatible RISC-V Softcore Processors","display_name":"A Catalog and In-Hardware Evaluation of Open-Source Drop-In Compatible RISC-V Softcore Processors","publication_year":2019,"publication_date":"2019-12-01","ids":{"openalex":"https://openalex.org/W3006305014","doi":"https://doi.org/10.1109/reconfig48160.2019.8994796","mag":"3006305014"},"language":"en","primary_location":{"id":"doi:10.1109/reconfig48160.2019.8994796","is_oa":false,"landing_page_url":"https://doi.org/10.1109/reconfig48160.2019.8994796","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 International Conference on ReConFigurable Computing and FPGAs (ReConFig)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5066519607","display_name":"Carsten Heinz","orcid":"https://orcid.org/0000-0001-5927-4426"},"institutions":[{"id":"https://openalex.org/I31512782","display_name":"Technical University of Darmstadt","ror":"https://ror.org/05n911h24","country_code":"DE","type":"education","lineage":["https://openalex.org/I31512782"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Carsten Heinz","raw_affiliation_strings":["Embedded Systems and Applications Group, TU Darmstadt, Darmstadt, Germany"],"affiliations":[{"raw_affiliation_string":"Embedded Systems and Applications Group, TU Darmstadt, Darmstadt, Germany","institution_ids":["https://openalex.org/I31512782"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5078275866","display_name":"Yannick Lavan","orcid":"https://orcid.org/0000-0001-5309-4141"},"institutions":[{"id":"https://openalex.org/I31512782","display_name":"Technical University of Darmstadt","ror":"https://ror.org/05n911h24","country_code":"DE","type":"education","lineage":["https://openalex.org/I31512782"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Yannick Lavan","raw_affiliation_strings":["Embedded Systems and Applications Group, TU Darmstadt, Darmstadt, Germany"],"affiliations":[{"raw_affiliation_string":"Embedded Systems and Applications Group, TU Darmstadt, Darmstadt, Germany","institution_ids":["https://openalex.org/I31512782"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5088361257","display_name":"Jaco Hofmann","orcid":"https://orcid.org/0000-0003-3691-3293"},"institutions":[{"id":"https://openalex.org/I31512782","display_name":"Technical University of Darmstadt","ror":"https://ror.org/05n911h24","country_code":"DE","type":"education","lineage":["https://openalex.org/I31512782"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Jaco Hofmann","raw_affiliation_strings":["Embedded Systems and Applications Group, TU Darmstadt, Darmstadt, Germany"],"affiliations":[{"raw_affiliation_string":"Embedded Systems and Applications Group, TU Darmstadt, Darmstadt, Germany","institution_ids":["https://openalex.org/I31512782"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5047000315","display_name":"Andreas Koch","orcid":"https://orcid.org/0000-0002-1164-3082"},"institutions":[{"id":"https://openalex.org/I31512782","display_name":"Technical University of Darmstadt","ror":"https://ror.org/05n911h24","country_code":"DE","type":"education","lineage":["https://openalex.org/I31512782"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Andreas Koch","raw_affiliation_strings":["Embedded Systems and Applications Group, TU Darmstadt, Darmstadt, Germany"],"affiliations":[{"raw_affiliation_string":"Embedded Systems and Applications Group, TU Darmstadt, Darmstadt, Germany","institution_ids":["https://openalex.org/I31512782"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5066519607"],"corresponding_institution_ids":["https://openalex.org/I31512782"],"apc_list":null,"apc_paid":null,"fwci":5.7784,"has_fulltext":false,"cited_by_count":45,"citation_normalized_percentile":{"value":0.96934516,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":96,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"8"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.798444390296936},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6652854681015015},{"id":"https://openalex.org/keywords/bitstream","display_name":"Bitstream","score":0.5765635967254639},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5365462303161621},{"id":"https://openalex.org/keywords/ranging","display_name":"Ranging","score":0.5337548851966858},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.4272356927394867},{"id":"https://openalex.org/keywords/task","display_name":"Task (project management)","score":0.4173718988895416},{"id":"https://openalex.org/keywords/reduced-instruction-set-computing","display_name":"Reduced instruction set computing","score":0.4166049361228943},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.390102744102478},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3820236921310425},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.35548949241638184},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.07326224446296692}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.798444390296936},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6652854681015015},{"id":"https://openalex.org/C136695289","wikidata":"https://www.wikidata.org/wiki/Q415568","display_name":"Bitstream","level":3,"score":0.5765635967254639},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5365462303161621},{"id":"https://openalex.org/C115051666","wikidata":"https://www.wikidata.org/wiki/Q6522493","display_name":"Ranging","level":2,"score":0.5337548851966858},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.4272356927394867},{"id":"https://openalex.org/C2780451532","wikidata":"https://www.wikidata.org/wiki/Q759676","display_name":"Task (project management)","level":2,"score":0.4173718988895416},{"id":"https://openalex.org/C126298526","wikidata":"https://www.wikidata.org/wiki/Q189376","display_name":"Reduced instruction set computing","level":3,"score":0.4166049361228943},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.390102744102478},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3820236921310425},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.35548949241638184},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.07326224446296692},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C57273362","wikidata":"https://www.wikidata.org/wiki/Q576722","display_name":"Decoding methods","level":2,"score":0.0},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/reconfig48160.2019.8994796","is_oa":false,"landing_page_url":"https://doi.org/10.1109/reconfig48160.2019.8994796","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 International Conference on ReConFigurable Computing and FPGAs (ReConFig)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.5799999833106995,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W2187802606","https://openalex.org/W2418145342","https://openalex.org/W2764252782","https://openalex.org/W2925940451","https://openalex.org/W6987020231","https://openalex.org/W6987144925"],"related_works":["https://openalex.org/W3217774925","https://openalex.org/W2040087757","https://openalex.org/W2497961712","https://openalex.org/W1989678405","https://openalex.org/W2588029177","https://openalex.org/W2766796104","https://openalex.org/W2076588311","https://openalex.org/W2399954712","https://openalex.org/W2901561495","https://openalex.org/W2990208673"],"abstract_inverted_index":{"With":[0],"the":[1,7,20,35,84,94,105,110,113,118,123,156,188],"increasing":[2],"popularity":[3],"of":[4,16,19,56,64,93,112,122,132,184,194],"RISC-V":[5,57,119],"in":[6,162,182],"academic":[8],"and":[9,47,75,98,135,150],"industrial":[10],"world,":[11],"an":[12,30,53],"ever":[13],"growing":[14],"number":[15,131],"open-source":[17,54],"implementations":[18],"instruction":[21],"set":[22],"have":[23,67,126,158],"become":[24],"available.":[25],"However,":[26],"it":[27],"is":[28],"not":[29],"easy":[31],"task":[32],"to":[33,37,107,203],"compare":[34],"cores":[36,58,66,125,157,167,180],"one":[38],"another,":[39],"as":[40,70,147],"they":[41],"employ":[42],"different":[43],"interconnects,":[44],"build":[45],"systems":[46],"so":[48],"on.":[49],"This":[50],"work":[51],"presents":[52],"catalog":[55],"for":[59,129],"use":[60],"on":[61,109,173],"FPGAs.":[62],"All":[63,121],"these":[65],"been":[68,127],"wrapped":[69],"drop-in":[71],"compatible":[72],"processing":[73],"elements":[74],"can":[76],"be":[77],"used":[78],"either":[79],"standalone,":[80],"or":[81],"integrated":[82],"into":[83],"TaPaSCo":[85],"SoC":[86],"composition":[87],"framework.":[88],"By":[89],"using":[90,141],"TaPaSCo,":[91],"details":[92],"bitstream":[95],"generation":[96],"flow":[97],"user-space":[99],"interfaces":[100],"are":[101,136],"abstracted":[102],"away,":[103],"allowing":[104],"user":[106],"focus":[108],"needs":[111],"concrete":[114],"applications":[115],"when":[116],"exploring":[117],"landscape.":[120],"catalog's":[124],"synthesized":[128],"a":[130,159,191],"hardware":[133],"platforms,":[134],"evaluated":[137],"against":[138],"each":[139],"other":[140],"state-of-the-art":[142],"embedded":[143],"processor":[144],"benchmarks":[145,189],"such":[146],"Dhrystone,":[148],"Embench":[149],"CoreMark.":[151],"The":[152,165],"results":[153],"show":[154,190],"that":[155],"huge":[160],"degree":[161],"performance":[163,195],"variability.":[164],"slowest":[166],"achieve":[168],"less":[169,198],"than":[170,199],"100":[171],"MHz":[172],"large":[174],"UltraScale+":[175],"devices,":[176],"while":[177],"better":[178],"FPGA-optimized":[179],"run":[181],"excess":[183],"500":[185],"MHz.":[186],"Accordingly,":[187],"wide":[192],"spread":[193],"ranging":[196],"from":[197],"0.5":[200],"CoreMark/MHz":[201],"up":[202],"over":[204],"2.5":[205],"CoreMark/MHz.":[206]},"counts_by_year":[{"year":2025,"cited_by_count":3},{"year":2024,"cited_by_count":12},{"year":2023,"cited_by_count":6},{"year":2022,"cited_by_count":10},{"year":2021,"cited_by_count":11},{"year":2020,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}