{"id":"https://openalex.org/W3005652835","doi":"https://doi.org/10.1109/reconfig48160.2019.8994693","title":"Seiba: An FPGA Overlay-Based Approach to Rapid Application Development","display_name":"Seiba: An FPGA Overlay-Based Approach to Rapid Application Development","publication_year":2019,"publication_date":"2019-12-01","ids":{"openalex":"https://openalex.org/W3005652835","doi":"https://doi.org/10.1109/reconfig48160.2019.8994693","mag":"3005652835"},"language":"en","primary_location":{"id":"doi:10.1109/reconfig48160.2019.8994693","is_oa":false,"landing_page_url":"https://doi.org/10.1109/reconfig48160.2019.8994693","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 International Conference on ReConFigurable Computing and FPGAs (ReConFig)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5102848731","display_name":"David Wilson","orcid":"https://orcid.org/0000-0002-6118-1250"},"institutions":[{"id":"https://openalex.org/I33213144","display_name":"University of Florida","ror":"https://ror.org/02y3ad647","country_code":"US","type":"education","lineage":["https://openalex.org/I33213144"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"David Wilson","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL, USA","institution_ids":["https://openalex.org/I33213144"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5088031457","display_name":"Greg Stitt","orcid":"https://orcid.org/0000-0001-7159-7439"},"institutions":[{"id":"https://openalex.org/I33213144","display_name":"University of Florida","ror":"https://ror.org/02y3ad647","country_code":"US","type":"education","lineage":["https://openalex.org/I33213144"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Greg Stitt","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL, USA","institution_ids":["https://openalex.org/I33213144"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5102848731"],"corresponding_institution_ids":["https://openalex.org/I33213144"],"apc_list":null,"apc_paid":null,"fwci":1.2038,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.78985129,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"8"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8311405181884766},{"id":"https://openalex.org/keywords/overlay","display_name":"Overlay","score":0.8113292455673218},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7986981868743896},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6240565776824951},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.6128497123718262},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5152011513710022},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.5099314451217651},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.47391045093536377},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.21664029359817505}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8311405181884766},{"id":"https://openalex.org/C136085584","wikidata":"https://www.wikidata.org/wiki/Q910289","display_name":"Overlay","level":2,"score":0.8113292455673218},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7986981868743896},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6240565776824951},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.6128497123718262},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5152011513710022},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.5099314451217651},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.47391045093536377},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.21664029359817505}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/reconfig48160.2019.8994693","is_oa":false,"landing_page_url":"https://doi.org/10.1109/reconfig48160.2019.8994693","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 International Conference on ReConFigurable Computing and FPGAs (ReConFig)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Decent work and economic growth","score":0.49000000953674316,"id":"https://metadata.un.org/sdg/8"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1886378107","https://openalex.org/W1970032753","https://openalex.org/W2052945447","https://openalex.org/W2105263017","https://openalex.org/W2136097861","https://openalex.org/W2472489786","https://openalex.org/W2473599928","https://openalex.org/W2788726558","https://openalex.org/W2894812787","https://openalex.org/W2904651897","https://openalex.org/W2950765666","https://openalex.org/W6720847456"],"related_works":["https://openalex.org/W2944879222","https://openalex.org/W2473515899","https://openalex.org/W2925002129","https://openalex.org/W2114354660","https://openalex.org/W2011469574","https://openalex.org/W2224499702","https://openalex.org/W1604320855","https://openalex.org/W2185500718","https://openalex.org/W3005652835","https://openalex.org/W2788424169"],"abstract_inverted_index":{"Although":[0],"high-level":[1,10],"synthesis":[2,11],"(HLS)":[3],"improves":[4],"designer":[5],"productivity":[6,104],"through":[7,112,117],"abstraction,":[8],"FPGA":[9,44,76,118,171],"stills":[12],"suffers":[13],"from":[14,142],"lengthy":[15],"compilation":[16,93],"that":[17,71,82,131,155],"limits":[18],"the":[19,59,158,168],"number":[20,169],"of":[21,32,170],"design":[22],"iterations":[23],"a":[24,91,127,174],"developer":[25],"can":[26,137,165],"achieve":[27],"per":[28],"day.":[29],"One":[30],"method":[31],"minimizing":[33],"these":[34],"compile":[35],"times":[36],"is":[37],"compiling":[38],"designs":[39],"with":[40,75],"innate":[41],"programmability,":[42],"aka":[43],"overlays,":[45],"and":[46,105,139],"using":[47],"their":[48],"runtime":[49,147,160],"configuration":[50,114,135],"to":[51,57,78,86,98,146],"implement":[52],"functional":[53,150],"changes,":[54],"as":[55],"opposed":[56],"recompiling":[58],"design.":[60],"In":[61],"this":[62,122],"paper,":[63],"we":[64],"introduce":[65],"Seiba,":[66],"an":[67,100,143],"application":[68,144],"development":[69,88,163,175],"approach":[70,125],"integrates":[72],"HLS":[73],"circuits":[74],"overlays":[77],"create":[79],"reconfigurable":[80],"platforms":[81],"are":[83],"rapidly":[84],"configured":[85],"reduce":[87,167],"time.":[89],"As":[90],"dual-layer":[92],"approach,":[94],"Seiba":[95],"enables":[96],"users":[97],"choose":[99],"appropriate":[101],"tradeoff":[102],"between":[103],"overhead":[106],"by":[107,156],"implementing":[108],"incremental":[109],"changes":[110],"quickly":[111],"overlay":[113,129,134,149],"or":[115],"efficiently":[116],"recompilation.":[119],"To":[120],"handle":[121],"integration,":[123],"our":[124,162],"uses":[126],"novel":[128],"architecture":[130],"offers":[132],"flexible":[133],"which":[136],"\u201cpatch\u201d":[138],"redirect":[140],"execution":[141],"circuit":[145],"configurable":[148],"units.":[151],"Our":[152],"results":[153],"show":[154],"leveraging":[157],"overlay's":[159],"configurability,":[161],"flow":[164],"significantly":[166],"compilations":[172],"in":[173],"cycle.":[176]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
