{"id":"https://openalex.org/W2912700011","doi":"https://doi.org/10.1109/reconfig.2018.8641736","title":"Model-Based Design Automation of Hardware/Software Co-Designs for Xilinx Zynq PSoCs","display_name":"Model-Based Design Automation of Hardware/Software Co-Designs for Xilinx Zynq PSoCs","publication_year":2018,"publication_date":"2018-12-01","ids":{"openalex":"https://openalex.org/W2912700011","doi":"https://doi.org/10.1109/reconfig.2018.8641736","mag":"2912700011"},"language":"en","primary_location":{"id":"doi:10.1109/reconfig.2018.8641736","is_oa":false,"landing_page_url":"https://doi.org/10.1109/reconfig.2018.8641736","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 International Conference on ReConFigurable Computing and FPGAs (ReConFig)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5019121790","display_name":"Franz-Josef Streit","orcid":"https://orcid.org/0000-0002-1063-1661"},"institutions":[{"id":"https://openalex.org/I181369854","display_name":"Friedrich-Alexander-Universit\u00e4t Erlangen-N\u00fcrnberg","ror":"https://ror.org/00f7hpc57","country_code":"DE","type":"education","lineage":["https://openalex.org/I181369854"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Franz-Josef Streit","raw_affiliation_strings":["Department of Computer Science 12, Friedrich-Alexander-Universit\u00e4t Erlangen-N\u00fcrnberg (FAU), Germany"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science 12, Friedrich-Alexander-Universit\u00e4t Erlangen-N\u00fcrnberg (FAU), Germany","institution_ids":["https://openalex.org/I181369854"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5053919772","display_name":"Mart\u00edn Letras","orcid":"https://orcid.org/0000-0002-1429-8982"},"institutions":[{"id":"https://openalex.org/I181369854","display_name":"Friedrich-Alexander-Universit\u00e4t Erlangen-N\u00fcrnberg","ror":"https://ror.org/00f7hpc57","country_code":"DE","type":"education","lineage":["https://openalex.org/I181369854"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Martin Letras","raw_affiliation_strings":["Department of Computer Science 12, Friedrich-Alexander-Universit\u00e4t Erlangen-N\u00fcrnberg (FAU), Germany"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science 12, Friedrich-Alexander-Universit\u00e4t Erlangen-N\u00fcrnberg (FAU), Germany","institution_ids":["https://openalex.org/I181369854"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5036056755","display_name":"Stefan Wildermann","orcid":"https://orcid.org/0000-0002-4324-2187"},"institutions":[{"id":"https://openalex.org/I181369854","display_name":"Friedrich-Alexander-Universit\u00e4t Erlangen-N\u00fcrnberg","ror":"https://ror.org/00f7hpc57","country_code":"DE","type":"education","lineage":["https://openalex.org/I181369854"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Stefan Wildermann","raw_affiliation_strings":["Department of Computer Science 12, Friedrich-Alexander-Universit\u00e4t Erlangen-N\u00fcrnberg (FAU), Germany"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science 12, Friedrich-Alexander-Universit\u00e4t Erlangen-N\u00fcrnberg (FAU), Germany","institution_ids":["https://openalex.org/I181369854"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5061333679","display_name":"Benjamin Hackenberg","orcid":null},"institutions":[{"id":"https://openalex.org/I181369854","display_name":"Friedrich-Alexander-Universit\u00e4t Erlangen-N\u00fcrnberg","ror":"https://ror.org/00f7hpc57","country_code":"DE","type":"education","lineage":["https://openalex.org/I181369854"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Benjamin Hackenberg","raw_affiliation_strings":["Department of Computer Science 12, Friedrich-Alexander-Universit\u00e4t Erlangen-N\u00fcrnberg (FAU), Germany"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science 12, Friedrich-Alexander-Universit\u00e4t Erlangen-N\u00fcrnberg (FAU), Germany","institution_ids":["https://openalex.org/I181369854"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5030647581","display_name":"Joachim Falk","orcid":"https://orcid.org/0009-0006-0834-3237"},"institutions":[{"id":"https://openalex.org/I181369854","display_name":"Friedrich-Alexander-Universit\u00e4t Erlangen-N\u00fcrnberg","ror":"https://ror.org/00f7hpc57","country_code":"DE","type":"education","lineage":["https://openalex.org/I181369854"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Joachim Falk","raw_affiliation_strings":["Department of Computer Science 12, Friedrich-Alexander-Universit\u00e4t Erlangen-N\u00fcrnberg (FAU), Germany"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science 12, Friedrich-Alexander-Universit\u00e4t Erlangen-N\u00fcrnberg (FAU), Germany","institution_ids":["https://openalex.org/I181369854"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5054355703","display_name":"Andreas Becher","orcid":"https://orcid.org/0000-0003-2750-7349"},"institutions":[{"id":"https://openalex.org/I181369854","display_name":"Friedrich-Alexander-Universit\u00e4t Erlangen-N\u00fcrnberg","ror":"https://ror.org/00f7hpc57","country_code":"DE","type":"education","lineage":["https://openalex.org/I181369854"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Andreas Becher","raw_affiliation_strings":["Department of Computer Science 12, Friedrich-Alexander-Universit\u00e4t Erlangen-N\u00fcrnberg (FAU), Germany"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science 12, Friedrich-Alexander-Universit\u00e4t Erlangen-N\u00fcrnberg (FAU), Germany","institution_ids":["https://openalex.org/I181369854"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5076672029","display_name":"J\u00fcrgen Teich","orcid":"https://orcid.org/0000-0001-6285-5862"},"institutions":[{"id":"https://openalex.org/I181369854","display_name":"Friedrich-Alexander-Universit\u00e4t Erlangen-N\u00fcrnberg","ror":"https://ror.org/00f7hpc57","country_code":"DE","type":"education","lineage":["https://openalex.org/I181369854"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Jurgen Teich","raw_affiliation_strings":["Department of Computer Science 12, Friedrich-Alexander-Universit\u00e4t Erlangen-N\u00fcrnberg (FAU), Germany"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science 12, Friedrich-Alexander-Universit\u00e4t Erlangen-N\u00fcrnberg (FAU), Germany","institution_ids":["https://openalex.org/I181369854"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":7,"corresponding_author_ids":["https://openalex.org/A5019121790"],"corresponding_institution_ids":["https://openalex.org/I181369854"],"apc_list":null,"apc_paid":null,"fwci":1.7673,"has_fulltext":false,"cited_by_count":11,"citation_normalized_percentile":{"value":0.85358103,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":"6","issue":null,"first_page":"1","last_page":"8"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12810","display_name":"Real-time simulation and control systems","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9976999759674072,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7225191593170166},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.7148203253746033},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6921008229255676},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.6739754676818848},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.5619570016860962},{"id":"https://openalex.org/keywords/model-based-design","display_name":"Model-based design","score":0.521167516708374},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.508857250213623},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.49136415123939514},{"id":"https://openalex.org/keywords/electronic-design-automation","display_name":"Electronic design automation","score":0.46951860189437866},{"id":"https://openalex.org/keywords/automation","display_name":"Automation","score":0.4281925559043884},{"id":"https://openalex.org/keywords/software-design","display_name":"Software design","score":0.4272410571575165},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.41467198729515076},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.36060184240341187},{"id":"https://openalex.org/keywords/software-development","display_name":"Software development","score":0.28579166531562805},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.17942523956298828},{"id":"https://openalex.org/keywords/simulation","display_name":"Simulation","score":0.1532737910747528},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.12757256627082825},{"id":"https://openalex.org/keywords/wireless","display_name":"Wireless","score":0.08248913288116455}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7225191593170166},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.7148203253746033},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6921008229255676},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.6739754676818848},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.5619570016860962},{"id":"https://openalex.org/C195672273","wikidata":"https://www.wikidata.org/wiki/Q6888132","display_name":"Model-based design","level":2,"score":0.521167516708374},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.508857250213623},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.49136415123939514},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.46951860189437866},{"id":"https://openalex.org/C115901376","wikidata":"https://www.wikidata.org/wiki/Q184199","display_name":"Automation","level":2,"score":0.4281925559043884},{"id":"https://openalex.org/C52913732","wikidata":"https://www.wikidata.org/wiki/Q857102","display_name":"Software design","level":4,"score":0.4272410571575165},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.41467198729515076},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.36060184240341187},{"id":"https://openalex.org/C529173508","wikidata":"https://www.wikidata.org/wiki/Q638608","display_name":"Software development","level":3,"score":0.28579166531562805},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.17942523956298828},{"id":"https://openalex.org/C44154836","wikidata":"https://www.wikidata.org/wiki/Q45045","display_name":"Simulation","level":1,"score":0.1532737910747528},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.12757256627082825},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.08248913288116455},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/reconfig.2018.8641736","is_oa":false,"landing_page_url":"https://doi.org/10.1109/reconfig.2018.8641736","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 International Conference on ReConFigurable Computing and FPGAs (ReConFig)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1587874771","https://openalex.org/W2029518208","https://openalex.org/W2064115172","https://openalex.org/W2078830317","https://openalex.org/W2111413831","https://openalex.org/W2144170715","https://openalex.org/W2313278055","https://openalex.org/W2616012601","https://openalex.org/W2770023641","https://openalex.org/W6635277882"],"related_works":["https://openalex.org/W3011978806","https://openalex.org/W3204573923","https://openalex.org/W3207169898","https://openalex.org/W3198354237","https://openalex.org/W2743305891","https://openalex.org/W4385309418","https://openalex.org/W2331259470","https://openalex.org/W2019954703","https://openalex.org/W2059530328","https://openalex.org/W2535520145"],"abstract_inverted_index":{"Shorter":[0],"design":[1,14,28,56,61,107,160],"cycles":[2],"in":[3,43,99],"FPGA-based":[4],"Programmable":[5],"System-on-Chips":[6],"(PSoCs)":[7],"development":[8],"require":[9],"a":[10,20,40,95,105,121,145,149,154],"higher":[11],"level":[12],"of":[13,23,31,88,124,171],"automation,":[15],"which":[16,109],"has":[17],"led":[18],"to":[19,47,78,135,167],"wide":[21],"acceptance":[22],"model":[24],"driven":[25],"engineering.":[26],"However,":[27],"and":[29,62,71,91,132,140,158,165],"implementation":[30,142],"applications":[32],"on":[33,120],"such":[34],"heterogeneous":[35],"PSoC":[36],"platforms":[37],"still":[38],"demand":[39],"comprehensive":[41],"expertise":[42],"hardware/software":[44,113],"co-design.":[45],"Therefore,":[46],"keep":[48],"up":[49],"with":[50,64],"this":[51,80],"trend,":[52],"an":[53],"automated":[54],"systematic":[55],"flow":[57,108],"that":[58],"couples":[59],"model-based":[60,100],"simulation":[63,92],"High-Level":[65],"Synthesis":[66],"(HLS)":[67],"for":[68,115],"hybrid":[69],"hardware":[70,139],"software":[72,141],"implementations":[73],"is":[74],"necessary.":[75],"In":[76],"order":[77],"address":[79],"issue,":[81],"the":[82,89,127,169],"work":[83],"at":[84],"hand":[85],"makes":[86],"use":[87],"modeling":[90],"environment":[93],"MATLAB/Simulink,":[94],"de":[96],"facto":[97],"standard":[98],"development.":[101],"Additionally,":[102],"we":[103,152],"present":[104,153],"novel":[106],"automatically":[110,136],"synthesizes":[111],"individual":[112],"solutions":[114],"Xilinx":[116],"Zynq":[117],"PSoCs":[118],"based":[119],"manual":[122],"partitioning":[123],"blocks.":[125],"Thereby,":[126],"proposed":[128],"methodology":[129],"enables":[130],"control":[131],"system":[133],"engineers":[134],"explore":[137],"different":[138],"variants":[143],"from":[144],"behavioral":[146],"model.":[147],"As":[148],"case":[150],"study,":[151],"JPEG":[155],"decoder":[156],"application":[157],"investigate":[159],"objectives":[161],"like":[162],"resource":[163],"costs":[164],"throughput":[166],"show":[168],"practicability":[170],"our":[172],"approach.":[173]},"counts_by_year":[{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":1},{"year":2020,"cited_by_count":5},{"year":2019,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
