{"id":"https://openalex.org/W2913411565","doi":"https://doi.org/10.1109/reconfig.2018.8641724","title":"Post-Routing Analytical Wirelength Model for Homogeneous FPGA Architectures","display_name":"Post-Routing Analytical Wirelength Model for Homogeneous FPGA Architectures","publication_year":2018,"publication_date":"2018-12-01","ids":{"openalex":"https://openalex.org/W2913411565","doi":"https://doi.org/10.1109/reconfig.2018.8641724","mag":"2913411565"},"language":"en","primary_location":{"id":"doi:10.1109/reconfig.2018.8641724","is_oa":false,"landing_page_url":"https://doi.org/10.1109/reconfig.2018.8641724","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 International Conference on ReConFigurable Computing and FPGAs (ReConFig)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5016067692","display_name":"Arpit Soni","orcid":null},"institutions":[{"id":"https://openalex.org/I138006243","display_name":"University of Arizona","ror":"https://ror.org/03m2x1q45","country_code":"US","type":"education","lineage":["https://openalex.org/I138006243"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Arpit Soni","raw_affiliation_strings":["Electrical and Computer Engineering, University of Arizona, Tucson, AZ, USA"],"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering, University of Arizona, Tucson, AZ, USA","institution_ids":["https://openalex.org/I138006243"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5048384811","display_name":"Yoon Kah Leow","orcid":null},"institutions":[{"id":"https://openalex.org/I138006243","display_name":"University of Arizona","ror":"https://ror.org/03m2x1q45","country_code":"US","type":"education","lineage":["https://openalex.org/I138006243"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yoon Kah Leow","raw_affiliation_strings":["Electrical and Computer Engineering, University of Arizona, Tucson, AZ, USA"],"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering, University of Arizona, Tucson, AZ, USA","institution_ids":["https://openalex.org/I138006243"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5080974820","display_name":"Ali Akoglu","orcid":"https://orcid.org/0000-0001-7982-8991"},"institutions":[{"id":"https://openalex.org/I138006243","display_name":"University of Arizona","ror":"https://ror.org/03m2x1q45","country_code":"US","type":"education","lineage":["https://openalex.org/I138006243"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ali Akoglu","raw_affiliation_strings":["Electrical and Computer Engineering, University of Arizona, Tucson, AZ, USA"],"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering, University of Arizona, Tucson, AZ, USA","institution_ids":["https://openalex.org/I138006243"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5016067692"],"corresponding_institution_ids":["https://openalex.org/I138006243"],"apc_list":null,"apc_paid":null,"fwci":0.1288,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.52022384,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"45","issue":null,"first_page":"1","last_page":"8"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/netlist","display_name":"Netlist","score":0.9755621552467346},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.7563345432281494},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6797884702682495},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6569426655769348},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.5200504660606384},{"id":"https://openalex.org/keywords/placement","display_name":"Placement","score":0.4432831406593323},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4279457628726959},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4207269549369812},{"id":"https://openalex.org/keywords/electronic-design-automation","display_name":"Electronic design automation","score":0.4190274775028229},{"id":"https://openalex.org/keywords/standard-cell","display_name":"Standard cell","score":0.4155893921852112},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.3533584475517273},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3451464772224426},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.3411954641342163},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.2843743562698364},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.1630626618862152},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.14246916770935059}],"concepts":[{"id":"https://openalex.org/C177650935","wikidata":"https://www.wikidata.org/wiki/Q1760303","display_name":"Netlist","level":2,"score":0.9755621552467346},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.7563345432281494},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6797884702682495},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6569426655769348},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.5200504660606384},{"id":"https://openalex.org/C117690923","wikidata":"https://www.wikidata.org/wiki/Q1484784","display_name":"Placement","level":4,"score":0.4432831406593323},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4279457628726959},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4207269549369812},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.4190274775028229},{"id":"https://openalex.org/C78401558","wikidata":"https://www.wikidata.org/wiki/Q464496","display_name":"Standard cell","level":3,"score":0.4155893921852112},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.3533584475517273},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3451464772224426},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3411954641342163},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2843743562698364},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.1630626618862152},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.14246916770935059},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/reconfig.2018.8641724","is_oa":false,"landing_page_url":"https://doi.org/10.1109/reconfig.2018.8641724","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 International Conference on ReConFigurable Computing and FPGAs (ReConFig)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.5,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":34,"referenced_works":["https://openalex.org/W1594570581","https://openalex.org/W1970296212","https://openalex.org/W1976144991","https://openalex.org/W1989477191","https://openalex.org/W1991530123","https://openalex.org/W1996478743","https://openalex.org/W2005275470","https://openalex.org/W2005602803","https://openalex.org/W2023428606","https://openalex.org/W2024174517","https://openalex.org/W2028954821","https://openalex.org/W2029853052","https://openalex.org/W2069712919","https://openalex.org/W2097521167","https://openalex.org/W2101356024","https://openalex.org/W2102503881","https://openalex.org/W2106814045","https://openalex.org/W2110265185","https://openalex.org/W2111158608","https://openalex.org/W2111756578","https://openalex.org/W2115402073","https://openalex.org/W2131696304","https://openalex.org/W2138383740","https://openalex.org/W2146306637","https://openalex.org/W2150766099","https://openalex.org/W2164340799","https://openalex.org/W2169510384","https://openalex.org/W2342306796","https://openalex.org/W4241249008","https://openalex.org/W4251656018","https://openalex.org/W6635508542","https://openalex.org/W6654579118","https://openalex.org/W6704437296","https://openalex.org/W6995824316"],"related_works":["https://openalex.org/W2169510384","https://openalex.org/W2171793444","https://openalex.org/W2066616140","https://openalex.org/W2503215586","https://openalex.org/W2543084892","https://openalex.org/W2077246255","https://openalex.org/W4386859294","https://openalex.org/W2024392966","https://openalex.org/W1966563007","https://openalex.org/W1513389318"],"abstract_inverted_index":{"We":[0,54],"present":[1],"a":[2,16,82,105],"post-routing":[3,93],"model":[4,21],"that":[5],"relates":[6],"both":[7],"logic":[8],"and":[9,46,75,96],"routing":[10],"architecture":[11],"parameters":[12],"to":[13,66],"wirelength":[14],"for":[15,91],"homogeneous":[17],"FPGA":[18,51],"architecture.":[19],"Our":[20],"relies":[22],"on":[23],"Rent's":[24],"parameter":[25],"generated":[26],"from":[27,39],"the":[28,43,50,67,89],"pre-technology":[29],"mapped":[30],"netlist":[31,35],"rather":[32],"than":[33],"post-placement":[34],"making":[36],"it":[37],"independent":[38],"optimization":[40],"goal":[41],"of":[42,49,63,84,107],"technology-mapping,":[44],"clustering":[45],"placement":[47],"stages":[48],"CAD":[52],"flow.":[53],"achieve":[55],"an":[56],"average":[57],"mean":[58],"absolute":[59],"percentage":[60],"error":[61],"(MAPE)":[62],"36%":[64],"relative":[65],"Verilog-to-Routing":[68],"(VTR)":[69],"based":[70],"wire-length":[71],"analysis":[72],"using":[73],"MCNC":[74],"VTR":[76],"benchmarks,":[77],"while":[78],"state-of-the-art":[79],"approach":[80],"achieves":[81],"MAPE":[83],"57%.":[85],"This":[86],"work":[87],"forms":[88],"basis":[90],"implementing":[92],"delay,":[94],"routability":[95],"power":[97],"models,":[98],"since":[99],"each":[100],"can":[101],"be":[102],"expressed":[103],"as":[104],"function":[106],"net":[108],"length.":[109]},"counts_by_year":[{"year":2020,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}