{"id":"https://openalex.org/W2914831004","doi":"https://doi.org/10.1109/reconfig.2018.8641698","title":"Using Runtime Circuit Specialization to Accelerate Simulations of Reconfigurable Architectures","display_name":"Using Runtime Circuit Specialization to Accelerate Simulations of Reconfigurable Architectures","publication_year":2018,"publication_date":"2018-12-01","ids":{"openalex":"https://openalex.org/W2914831004","doi":"https://doi.org/10.1109/reconfig.2018.8641698","mag":"2914831004"},"language":"en","primary_location":{"id":"doi:10.1109/reconfig.2018.8641698","is_oa":false,"landing_page_url":"https://doi.org/10.1109/reconfig.2018.8641698","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 International Conference on ReConFigurable Computing and FPGAs (ReConFig)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5052101520","display_name":"Dillon Huff","orcid":"https://orcid.org/0000-0001-9055-3490"},"institutions":[{"id":"https://openalex.org/I97018004","display_name":"Stanford University","ror":"https://ror.org/00f54p054","country_code":"US","type":"education","lineage":["https://openalex.org/I97018004"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Dillon Huff","raw_affiliation_strings":["Department of Computer Science, Stanford University"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, Stanford University","institution_ids":["https://openalex.org/I97018004"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5018111215","display_name":"Pat Hanrahan","orcid":"https://orcid.org/0000-0002-3474-9752"},"institutions":[{"id":"https://openalex.org/I97018004","display_name":"Stanford University","ror":"https://ror.org/00f54p054","country_code":"US","type":"education","lineage":["https://openalex.org/I97018004"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Pat Hanrahan","raw_affiliation_strings":["Department of Computer Science, Stanford University"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, Stanford University","institution_ids":["https://openalex.org/I97018004"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5052101520"],"corresponding_institution_ids":["https://openalex.org/I97018004"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.20031777,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"25","issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7888178825378418},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6285686492919922},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.620891273021698},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5267937779426575},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.49164825677871704},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.4897020161151886},{"id":"https://openalex.org/keywords/computer-architecture-simulator","display_name":"Computer architecture simulator","score":0.4339870810508728},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4248313903808594},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3230017125606537}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7888178825378418},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6285686492919922},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.620891273021698},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5267937779426575},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.49164825677871704},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.4897020161151886},{"id":"https://openalex.org/C201203610","wikidata":"https://www.wikidata.org/wiki/Q5157524","display_name":"Computer architecture simulator","level":2,"score":0.4339870810508728},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4248313903808594},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3230017125606537},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/reconfig.2018.8641698","is_oa":false,"landing_page_url":"https://doi.org/10.1109/reconfig.2018.8641698","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 International Conference on ReConFigurable Computing and FPGAs (ReConFig)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Sustainable cities and communities","score":0.5099999904632568,"id":"https://metadata.un.org/sdg/11"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W136674180","https://openalex.org/W1556604985","https://openalex.org/W1895654053","https://openalex.org/W1986485435","https://openalex.org/W2000050212","https://openalex.org/W2015854972","https://openalex.org/W2038213124","https://openalex.org/W2083558835","https://openalex.org/W2111308925","https://openalex.org/W2116136092","https://openalex.org/W2149933188","https://openalex.org/W2152036980","https://openalex.org/W3140263950","https://openalex.org/W4237352773","https://openalex.org/W4245369543"],"related_works":["https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W1608572506","https://openalex.org/W3142211975","https://openalex.org/W2141090099","https://openalex.org/W1879443270","https://openalex.org/W2018912978","https://openalex.org/W2130914040","https://openalex.org/W2119122672","https://openalex.org/W4292904049"],"abstract_inverted_index":{"Hardware":[0],"simulations":[1,7,165],"are":[2,11,141],"never":[3],"fast":[4],"enough,":[5],"and":[6],"of":[8,26,48,71,103,125,138,166],"reconfigurable":[9,31,168],"architectures":[10],"especially":[12],"slow.":[13],"The":[14,100],"problem":[15],"is":[16,33],"that":[17,22,53,156],"the":[18,27,46,72,77,98,104],"programmable":[19],"switching":[20],"network":[21],"takes":[23],"up":[24,142],"most":[25],"area":[28],"in":[29,133,146,150,164],"a":[30,49,68],"architecture":[32,73],"not":[34,109],"handled":[35],"well":[36],"by":[37,66],"modern":[38],"RTL":[39,51,101],"simulators.":[40,153],"In":[41],"this":[42,61,139],"paper":[43],"we":[44,118],"describe":[45],"design":[47,140],"new":[50],"simulator":[52,64,117,148],"uses":[54],"runtime":[55,157],"circuit":[56,158],"specialization":[57,159],"(RCS)":[58],"to":[59,95,97,111,121,143],"solve":[60],"problem.":[62],"Our":[63],"works":[65],"compiling":[67],"specialized":[69],"version":[70],"being":[74,79,106],"simulated":[75],"after":[76],"configuration":[78],"tested":[80,107],"has":[81],"been":[82],"loaded.":[83],"To":[84,114],"use":[85,119,132],"our":[86,116,147],"method":[87],"an":[88,126],"engineer":[89],"adds":[90],"small":[91],"hints":[92],"about":[93],"what":[94],"specialize":[96],"testbench.":[99],"description":[102],"chip":[105],"does":[108],"need":[110],"be":[112],"changed.":[113],"test":[115],"it":[120],"accelerate":[122],"regression":[123],"tests":[124],"island":[127],"style":[128],"CGRA":[129],"designed":[130],"for":[131],"image":[134],"processing.":[135],"Long":[136],"testbenches":[137],"6x":[144],"faster":[145],"than":[149],"state-of-the-art":[151],"commercial":[152],"We":[154],"believe":[155],"could":[160],"produce":[161],"similar":[162],"speedups":[163],"other":[167],"chips":[169],"as":[170],"well.":[171]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}