{"id":"https://openalex.org/W2787241561","doi":"https://doi.org/10.1109/reconfig.2017.8279807","title":"Rapid circuit-specific inlining tuning for FPGA high-level synthesis","display_name":"Rapid circuit-specific inlining tuning for FPGA high-level synthesis","publication_year":2017,"publication_date":"2017-12-01","ids":{"openalex":"https://openalex.org/W2787241561","doi":"https://doi.org/10.1109/reconfig.2017.8279807","mag":"2787241561"},"language":"en","primary_location":{"id":"doi:10.1109/reconfig.2017.8279807","is_oa":false,"landing_page_url":"https://doi.org/10.1109/reconfig.2017.8279807","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 International Conference on ReConFigurable Computing and FPGAs (ReConFig)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5016388595","display_name":"Daniel Holanda Noronha","orcid":"https://orcid.org/0000-0003-1043-0920"},"institutions":[{"id":"https://openalex.org/I141945490","display_name":"University of British Columbia","ror":"https://ror.org/03rmrcq20","country_code":"CA","type":"education","lineage":["https://openalex.org/I141945490"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"Daniel H. Noronha","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, Canada","institution_ids":["https://openalex.org/I141945490"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5070746947","display_name":"Jose P. Pinilla","orcid":null},"institutions":[{"id":"https://openalex.org/I141945490","display_name":"University of British Columbia","ror":"https://ror.org/03rmrcq20","country_code":"CA","type":"education","lineage":["https://openalex.org/I141945490"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Jose P. Pinilla","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, Canada","institution_ids":["https://openalex.org/I141945490"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5013246362","display_name":"Steven J. E. Wilton","orcid":"https://orcid.org/0000-0002-1241-6690"},"institutions":[{"id":"https://openalex.org/I141945490","display_name":"University of British Columbia","ror":"https://ror.org/03rmrcq20","country_code":"CA","type":"education","lineage":["https://openalex.org/I141945490"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Steven J. E. Wilton","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, Canada","institution_ids":["https://openalex.org/I141945490"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5016388595"],"corresponding_institution_ids":["https://openalex.org/I141945490"],"apc_list":null,"apc_paid":null,"fwci":0.6759,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.71460888,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":93,"max":97},"biblio":{"volume":"17","issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8452543616294861},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.807520866394043},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.6746171712875366},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6122034788131714},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5983786582946777},{"id":"https://openalex.org/keywords/optimizing-compiler","display_name":"Optimizing compiler","score":0.4693637192249298},{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.46581295132637024},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.4613649249076843},{"id":"https://openalex.org/keywords/metric","display_name":"Metric (unit)","score":0.4593418538570404},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3676406741142273},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3444260358810425},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.09719109535217285}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8452543616294861},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.807520866394043},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.6746171712875366},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6122034788131714},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5983786582946777},{"id":"https://openalex.org/C190902152","wikidata":"https://www.wikidata.org/wiki/Q1325106","display_name":"Optimizing compiler","level":3,"score":0.4693637192249298},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.46581295132637024},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.4613649249076843},{"id":"https://openalex.org/C176217482","wikidata":"https://www.wikidata.org/wiki/Q860554","display_name":"Metric (unit)","level":2,"score":0.4593418538570404},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3676406741142273},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3444260358810425},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.09719109535217285},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/reconfig.2017.8279807","is_oa":false,"landing_page_url":"https://doi.org/10.1109/reconfig.2017.8279807","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 International Conference on ReConFigurable Computing and FPGAs (ReConFig)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W1884563702","https://openalex.org/W1970032753","https://openalex.org/W2057807751","https://openalex.org/W2133156997","https://openalex.org/W4256629673"],"related_works":["https://openalex.org/W2002505081","https://openalex.org/W2083681681","https://openalex.org/W2778498407","https://openalex.org/W2577630842","https://openalex.org/W1172579163","https://openalex.org/W1488300410","https://openalex.org/W2138790427","https://openalex.org/W3146558274","https://openalex.org/W4246454774","https://openalex.org/W2162051035"],"abstract_inverted_index":{"Assumptions":[0],"about":[1],"the":[2,6,13,33,49,52,60,91,97,100,105,120,174],"underlying":[3],"architecture":[4],"of":[5,15,51,90,99,123,167],"target":[7,25],"hardware":[8],"is":[9,84,94,117,133],"typically":[10],"what":[11],"dictates":[12],"behavior":[14],"compiler":[16,115,179],"optimizations.":[17],"Nevertheless,":[18],"modern":[19],"high-level":[20],"synthesis":[21],"(HLS)":[22],"tools":[23],"that":[24,37,129],"field-programmable":[26],"gate":[27],"arrays":[28],"(FPGAs)":[29],"are":[30,108],"still":[31],"using":[32],"same":[34,175],"optimization":[35],"passes":[36],"were":[38],"developed":[39],"and":[40,63,86,96],"tuned":[41],"for":[42,80,103],"general":[43],"purpose":[44],"processors.":[45],"This":[46],"paper":[47],"examines":[48],"effect":[50,98],"inlining":[53,125],"pass":[54],"on":[55,59],"HLS-generated":[56],"hardware,":[57],"focusing":[58],"circuit":[61],"area":[62],"clock":[64,145,152],"cycles":[65,146],"metrics.":[66],"An":[67],"iterative":[68],"search":[69],"method":[70],"to":[71,77,135,157,171],"create":[72],"a":[73,113,130,165],"custom":[74],"inliner":[75,132,163],"tailored":[76],"each":[78,81],"benchmark":[79],"specific":[82],"metric":[83],"proposed":[85],"evaluated.":[87],"The":[88],"quality":[89],"results":[92],"generated":[93],"analyzed":[95],"coefficients":[101],"used":[102],"making":[104],"inline":[106],"decisions":[107],"also":[109],"separately":[110],"investigated.":[111],"Furthermore,":[112],"novel":[114],"cache":[116],"proposed,":[118],"enabling":[119],"rapid":[121],"evaluation":[122],"new":[124],"logic.":[126],"Results":[127],"show":[128],"circuit-specific":[131],"able":[134],"generate":[136],"circuits":[137],"with":[138],"either":[139],"6%":[140],"fewer":[141,144],"LEs,":[142],"15%":[143],"or":[147],"11%":[148],"smaller":[149],"LEs":[150],"*":[151],"cycle":[153],"product":[154],"when":[155,169],"compared":[156,170],"LLVM's":[158],"default":[159],"approach.":[160],"Moreover,":[161],"our":[162],"achieved":[164],"speedup":[166],"23x":[168],"LLVM":[172],"performing":[173],"task":[176],"without":[177],".the":[178],"cache.":[180]},"counts_by_year":[{"year":2021,"cited_by_count":2},{"year":2019,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}