{"id":"https://openalex.org/W2787838238","doi":"https://doi.org/10.1109/reconfig.2017.8279789","title":"Evaluation of CGRA architecture for real-time processing of biological signals on wearable devices","display_name":"Evaluation of CGRA architecture for real-time processing of biological signals on wearable devices","publication_year":2017,"publication_date":"2017-12-01","ids":{"openalex":"https://openalex.org/W2787838238","doi":"https://doi.org/10.1109/reconfig.2017.8279789","mag":"2787838238"},"language":"en","primary_location":{"id":"doi:10.1109/reconfig.2017.8279789","is_oa":false,"landing_page_url":"https://doi.org/10.1109/reconfig.2017.8279789","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 International Conference on ReConFigurable Computing and FPGAs (ReConFig)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5037286094","display_name":"Jo\u00e3o D. Lopes","orcid":"https://orcid.org/0000-0002-8903-9715"},"institutions":[{"id":"https://openalex.org/I4210166615","display_name":"INESC TEC","ror":"https://ror.org/05fa8ka61","country_code":"PT","type":"nonprofit","lineage":["https://openalex.org/I4210125590","https://openalex.org/I4210166615"]},{"id":"https://openalex.org/I182534213","display_name":"Universidade do Porto","ror":"https://ror.org/043pwc612","country_code":"PT","type":"education","lineage":["https://openalex.org/I182534213"]}],"countries":["PT"],"is_corresponding":true,"raw_author_name":"Joao Lopes","raw_affiliation_strings":["INESC TEC and Faculty of Engineering, University of Porto, Porto, Portugal"],"affiliations":[{"raw_affiliation_string":"INESC TEC and Faculty of Engineering, University of Porto, Porto, Portugal","institution_ids":["https://openalex.org/I4210166615","https://openalex.org/I182534213"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5019965334","display_name":"Diogo Sousa","orcid":null},"institutions":[{"id":"https://openalex.org/I182534213","display_name":"Universidade do Porto","ror":"https://ror.org/043pwc612","country_code":"PT","type":"education","lineage":["https://openalex.org/I182534213"]},{"id":"https://openalex.org/I4210166615","display_name":"INESC TEC","ror":"https://ror.org/05fa8ka61","country_code":"PT","type":"nonprofit","lineage":["https://openalex.org/I4210125590","https://openalex.org/I4210166615"]}],"countries":["PT"],"is_corresponding":false,"raw_author_name":"Diogo Sousa","raw_affiliation_strings":["INESC TEC and Faculty of Engineering, University of Porto, Porto, Portugal"],"affiliations":[{"raw_affiliation_string":"INESC TEC and Faculty of Engineering, University of Porto, Porto, Portugal","institution_ids":["https://openalex.org/I4210166615","https://openalex.org/I182534213"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5107062770","display_name":"Jo\u00e3o Canas Ferreira","orcid":"https://orcid.org/0000-0001-7471-3888"},"institutions":[{"id":"https://openalex.org/I4210166615","display_name":"INESC TEC","ror":"https://ror.org/05fa8ka61","country_code":"PT","type":"nonprofit","lineage":["https://openalex.org/I4210125590","https://openalex.org/I4210166615"]},{"id":"https://openalex.org/I182534213","display_name":"Universidade do Porto","ror":"https://ror.org/043pwc612","country_code":"PT","type":"education","lineage":["https://openalex.org/I182534213"]}],"countries":["PT"],"is_corresponding":false,"raw_author_name":"Joao Canas Ferreira","raw_affiliation_strings":["INESC TEC and Faculty of Engineering, University of Porto, Porto, Portugal"],"affiliations":[{"raw_affiliation_string":"INESC TEC and Faculty of Engineering, University of Porto, Porto, Portugal","institution_ids":["https://openalex.org/I4210166615","https://openalex.org/I182534213"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5037286094"],"corresponding_institution_ids":["https://openalex.org/I182534213","https://openalex.org/I4210166615"],"apc_list":null,"apc_paid":null,"fwci":1.1266,"has_fulltext":false,"cited_by_count":15,"citation_normalized_percentile":{"value":0.80545303,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9973000288009644,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7323399186134338},{"id":"https://openalex.org/keywords/power-gating","display_name":"Power gating","score":0.62613844871521},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5859553813934326},{"id":"https://openalex.org/keywords/node","display_name":"Node (physics)","score":0.5439453721046448},{"id":"https://openalex.org/keywords/signal-processing","display_name":"Signal processing","score":0.5273056030273438},{"id":"https://openalex.org/keywords/wearable-computer","display_name":"Wearable computer","score":0.4941437542438507},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.48170167207717896},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.47470182180404663},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.4553440809249878},{"id":"https://openalex.org/keywords/signal","display_name":"SIGNAL (programming language)","score":0.43491077423095703},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.43014290928840637},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.39071124792099},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.17828956246376038},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.16492977738380432},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.15116724371910095},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.09063220024108887},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.07321220636367798}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7323399186134338},{"id":"https://openalex.org/C2780700455","wikidata":"https://www.wikidata.org/wiki/Q7236515","display_name":"Power gating","level":4,"score":0.62613844871521},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5859553813934326},{"id":"https://openalex.org/C62611344","wikidata":"https://www.wikidata.org/wiki/Q1062658","display_name":"Node (physics)","level":2,"score":0.5439453721046448},{"id":"https://openalex.org/C104267543","wikidata":"https://www.wikidata.org/wiki/Q208163","display_name":"Signal processing","level":3,"score":0.5273056030273438},{"id":"https://openalex.org/C150594956","wikidata":"https://www.wikidata.org/wiki/Q1334829","display_name":"Wearable computer","level":2,"score":0.4941437542438507},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.48170167207717896},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.47470182180404663},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.4553440809249878},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.43491077423095703},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.43014290928840637},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.39071124792099},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.17828956246376038},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.16492977738380432},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.15116724371910095},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.09063220024108887},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.07321220636367798},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C66938386","wikidata":"https://www.wikidata.org/wiki/Q633538","display_name":"Structural engineering","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/reconfig.2017.8279789","is_oa":false,"landing_page_url":"https://doi.org/10.1109/reconfig.2017.8279789","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 International Conference on ReConFigurable Computing and FPGAs (ReConFig)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8999999761581421}],"awards":[],"funders":[{"id":"https://openalex.org/F4320335322","display_name":"European Regional Development Fund","ror":"https://ror.org/00k4n6c32"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W93901327","https://openalex.org/W1563549564","https://openalex.org/W1997033495","https://openalex.org/W2012609332","https://openalex.org/W2014198201","https://openalex.org/W2047049615","https://openalex.org/W2099086364","https://openalex.org/W2122708981","https://openalex.org/W2134673133","https://openalex.org/W2162273778","https://openalex.org/W2164082066","https://openalex.org/W2165052329","https://openalex.org/W2167747774","https://openalex.org/W2411311483","https://openalex.org/W2530519012","https://openalex.org/W2746839058","https://openalex.org/W4246246179","https://openalex.org/W6684098564"],"related_works":["https://openalex.org/W2138099459","https://openalex.org/W2140707386","https://openalex.org/W2339195741","https://openalex.org/W1965635593","https://openalex.org/W4210367193","https://openalex.org/W4249785026","https://openalex.org/W2041557219","https://openalex.org/W2133075121","https://openalex.org/W2113682982","https://openalex.org/W2984119185"],"abstract_inverted_index":{"This":[0],"paper":[1],"describes":[2],"the":[3,25,52,123],"design":[4,67],"and":[5,28,76],"implementation":[6],"of":[7,86,99,122],"a":[8,40,44],"coarse-grained":[9],"reconfigurable":[10],"array":[11],"(CGRA)":[12],"for":[13,70,110],"low-power":[14],"biological":[15],"signal":[16,89],"processing.":[17],"It":[18],"uses":[19],"an":[20,95],"use-case-driven":[21],"approach":[22],"which":[23],"explores":[24],"application":[26],"domain":[27],"gathers":[29],"common":[30],"requirements.":[31],"The":[32,64,81],"selected":[33,65],"CGRA":[34,53,66,124],"core":[35],"architecture":[36],"is":[37,68,84],"implemented":[38],"using":[39,73,118],"standard-cell":[41],"flow":[42],"(in":[43],"generic":[45],"90":[46],"nm":[47],"CMOS":[48],"process),":[49],"so":[50],"that":[51],"can":[54,114],"be":[55,115],"totally":[56],"or":[57],"partially":[58],"turned":[59],"off":[60],"by":[61,117],"power":[62,97,108],"gating.":[63],"evaluated":[69],"two":[71],"use-cases":[72],"layout":[74],"information":[75],"accurate":[77],"node":[78],"activity":[79],"information.":[80],"resulting":[82],"accelerator":[83],"capable":[85],"performing":[87],"various":[88],"processing":[90],"tasks":[91,113],"very":[92],"efficiently,":[93],"achieving":[94],"average":[96],"consumption":[98,109],"19.9pJ/cycle":[100],"(or":[101],"1.99":[102],"mW":[103],"at":[104],"100":[105],"MHz).":[106],"Static":[107],"less":[111],"intensive":[112],"reduced":[116],"only":[119],"some":[120],"sections":[121],"while":[125],"powering-off":[126],"others.":[127]},"counts_by_year":[{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":6},{"year":2020,"cited_by_count":2},{"year":2018,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
