{"id":"https://openalex.org/W2787037985","doi":"https://doi.org/10.1109/reconfig.2017.8279781","title":"Build fast, trade fast: FPGA-based high-frequency trading using high-level synthesis","display_name":"Build fast, trade fast: FPGA-based high-frequency trading using high-level synthesis","publication_year":2017,"publication_date":"2017-12-01","ids":{"openalex":"https://openalex.org/W2787037985","doi":"https://doi.org/10.1109/reconfig.2017.8279781","mag":"2787037985"},"language":"en","primary_location":{"id":"doi:10.1109/reconfig.2017.8279781","is_oa":false,"landing_page_url":"https://doi.org/10.1109/reconfig.2017.8279781","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 International Conference on ReConFigurable Computing and FPGAs (ReConFig)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5090801235","display_name":"Andrew Boutros","orcid":"https://orcid.org/0000-0002-8044-1644"},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"Andrew Boutros","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Toronto"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Toronto","institution_ids":["https://openalex.org/I185261750"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5033542236","display_name":"Brett Grady","orcid":null},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Brett Grady","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Toronto"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Toronto","institution_ids":["https://openalex.org/I185261750"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5022371258","display_name":"Mustafa Abbas","orcid":null},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Mustafa Abbas","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Toronto"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Toronto","institution_ids":["https://openalex.org/I185261750"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5035437657","display_name":"Paul Chow","orcid":"https://orcid.org/0000-0002-0523-7117"},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Paul Chow","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Toronto"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Toronto","institution_ids":["https://openalex.org/I185261750"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5090801235"],"corresponding_institution_ids":["https://openalex.org/I185261750"],"apc_list":null,"apc_paid":null,"fwci":0.4542,"has_fulltext":false,"cited_by_count":27,"citation_normalized_percentile":{"value":0.68002297,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9904999732971191,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9904999732971191,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9902999997138977,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10232","display_name":"Optical Network Technologies","score":0.9836999773979187,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.81158447265625},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8091181516647339},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.6572125554084778},{"id":"https://openalex.org/keywords/high-frequency-trading","display_name":"High-frequency trading","score":0.6025410890579224},{"id":"https://openalex.org/keywords/implementation","display_name":"Implementation","score":0.6010695695877075},{"id":"https://openalex.org/keywords/low-latency","display_name":"Low latency (capital markets)","score":0.5690557956695557},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5476396083831787},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.4758971631526947},{"id":"https://openalex.org/keywords/arm-architecture","display_name":"ARM architecture","score":0.4553719758987427},{"id":"https://openalex.org/keywords/time-to-market","display_name":"Time to market","score":0.45087453722953796},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.43731608986854553},{"id":"https://openalex.org/keywords/protocol-stack","display_name":"Protocol stack","score":0.4317091107368469},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.4141799509525299},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.32726383209228516},{"id":"https://openalex.org/keywords/algorithmic-trading","display_name":"Algorithmic trading","score":0.3079918622970581},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.24220529198646545},{"id":"https://openalex.org/keywords/stack","display_name":"Stack (abstract data type)","score":0.17968344688415527},{"id":"https://openalex.org/keywords/software-engineering","display_name":"Software engineering","score":0.1235605776309967},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.11769583821296692},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.09025886654853821}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.81158447265625},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8091181516647339},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.6572125554084778},{"id":"https://openalex.org/C24683644","wikidata":"https://www.wikidata.org/wiki/Q138372","display_name":"High-frequency trading","level":3,"score":0.6025410890579224},{"id":"https://openalex.org/C26713055","wikidata":"https://www.wikidata.org/wiki/Q245962","display_name":"Implementation","level":2,"score":0.6010695695877075},{"id":"https://openalex.org/C46637626","wikidata":"https://www.wikidata.org/wiki/Q6693015","display_name":"Low latency (capital markets)","level":2,"score":0.5690557956695557},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5476396083831787},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.4758971631526947},{"id":"https://openalex.org/C26771161","wikidata":"https://www.wikidata.org/wiki/Q16980","display_name":"ARM architecture","level":2,"score":0.4553719758987427},{"id":"https://openalex.org/C2779229675","wikidata":"https://www.wikidata.org/wiki/Q445235","display_name":"Time to market","level":2,"score":0.45087453722953796},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.43731608986854553},{"id":"https://openalex.org/C38601921","wikidata":"https://www.wikidata.org/wiki/Q1757693","display_name":"Protocol stack","level":3,"score":0.4317091107368469},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.4141799509525299},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.32726383209228516},{"id":"https://openalex.org/C78508483","wikidata":"https://www.wikidata.org/wiki/Q139445","display_name":"Algorithmic trading","level":2,"score":0.3079918622970581},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.24220529198646545},{"id":"https://openalex.org/C9395851","wikidata":"https://www.wikidata.org/wiki/Q177929","display_name":"Stack (abstract data type)","level":2,"score":0.17968344688415527},{"id":"https://openalex.org/C115903868","wikidata":"https://www.wikidata.org/wiki/Q80993","display_name":"Software engineering","level":1,"score":0.1235605776309967},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.11769583821296692},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.09025886654853821},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C10138342","wikidata":"https://www.wikidata.org/wiki/Q43015","display_name":"Finance","level":1,"score":0.0},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/reconfig.2017.8279781","is_oa":false,"landing_page_url":"https://doi.org/10.1109/reconfig.2017.8279781","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 International Conference on ReConFigurable Computing and FPGAs (ReConFig)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.6499999761581421,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320322015","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1563299586","https://openalex.org/W1978514359","https://openalex.org/W2060331219","https://openalex.org/W2072172623","https://openalex.org/W2073373168","https://openalex.org/W2102596689","https://openalex.org/W2108381092","https://openalex.org/W2112096462","https://openalex.org/W2115302999","https://openalex.org/W2139241970","https://openalex.org/W2278396229","https://openalex.org/W2508078667","https://openalex.org/W2697402822","https://openalex.org/W6677271529","https://openalex.org/W6724763904"],"related_works":["https://openalex.org/W2504476032","https://openalex.org/W2068415504","https://openalex.org/W4221029479","https://openalex.org/W4206804280","https://openalex.org/W2888348582","https://openalex.org/W2341951110","https://openalex.org/W2098534862","https://openalex.org/W2300030311","https://openalex.org/W2555717339","https://openalex.org/W2955432270"],"abstract_inverted_index":{"High-Frequency":[0],"Trading":[1],"(HFT)":[2],"systems":[3],"require":[4],"extremely":[5],"low":[6],"latency":[7,141],"in":[8,83,104],"response":[9],"to":[10,22,60,99,113,148],"market":[11],"updates.":[12],"This":[13],"motivates":[14],"the":[15,29,44,114,117],"use":[16],"of":[17,47,116],"Field-Programmable":[18],"Gate":[19],"Arrays":[20],"(FPGAs)":[21],"accelerate":[23],"different":[24],"system":[25,81,123,158],"components":[26,82],"such":[27,62],"as":[28],"network":[30],"stack,":[31],"financial":[32],"protocol":[33],"parsing,":[34],"order":[35],"book":[36],"handling":[37],"and":[38,49,109,161],"even":[39],"custom":[40],"trading":[41,102],"algorithms.":[42],"However,":[43],"long":[45],"cycle":[46],"developing":[48],"verifying":[50],"FPGA":[51,129],"designs":[52],"makes":[53],"it":[54,112],"challenging":[55],"for":[56],"HFT":[57,96],"software":[58],"developers":[59,98],"deploy":[61],"highly-dynamic":[63],"systems,":[64],"especially":[65],"with":[66],"their":[67,101],"limited":[68],"hardware":[69],"design":[70],"expertise.":[71],"We":[72,89,119],"present":[73],"a":[74,92,105,125],"complete":[75],"highly-optimized":[76],"infrastructure":[77],"that":[78,94,149],"implements":[79],"low-latency":[80],"C++":[84],"using":[85],"High-Level":[86],"Synthesis":[87],"(HLS).":[88],"also":[90],"develop":[91],"framework":[93],"enables":[95],"algorithm":[97],"implement":[100],"algorithms":[103],"high-level":[106],"programming":[107],"language":[108],"rapidly":[110],"integrate":[111],"rest":[115],"system.":[118],"implemented":[120],"our":[121],"HLS-based":[122],"on":[124],"Xilinx":[126],"Kintex":[127],"Ultrascale":[128],"running":[130],"at":[131],"156":[132],"MHz.":[133],"Our":[134],"on-board":[135],"measurements":[136],"show":[137],"an":[138],"end-to-end":[139],"round-trip":[140],"less":[142],"than":[143],"870ns,":[144],"which":[145],"is":[146],"comparable":[147],"achieved":[150],"by":[151],"prior":[152],"RTL-based":[153],"implementations":[154],"but":[155],"requires":[156],"reduced":[157],"development":[159],"time":[160],"effort.":[162]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":7},{"year":2022,"cited_by_count":11},{"year":2021,"cited_by_count":4},{"year":2019,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}