{"id":"https://openalex.org/W2786401676","doi":"https://doi.org/10.1109/reconfig.2017.8279779","title":"A Dynamically Reconfigurable Automata Processor Overlay","display_name":"A Dynamically Reconfigurable Automata Processor Overlay","publication_year":2017,"publication_date":"2017-12-01","ids":{"openalex":"https://openalex.org/W2786401676","doi":"https://doi.org/10.1109/reconfig.2017.8279779","mag":"2786401676"},"language":"en","primary_location":{"id":"doi:10.1109/reconfig.2017.8279779","is_oa":false,"landing_page_url":"https://doi.org/10.1109/reconfig.2017.8279779","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 International Conference on ReConFigurable Computing and FPGAs (ReConFig)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5086678276","display_name":"Rasha Karakchi","orcid":"https://orcid.org/0009-0004-1391-0166"},"institutions":[{"id":"https://openalex.org/I155781252","display_name":"University of South Carolina","ror":"https://ror.org/02b6qw903","country_code":"US","type":"education","lineage":["https://openalex.org/I155781252"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Rasha Karakchi","raw_affiliation_strings":["Dept. of Computer Science and Engineering, Univ. of South Carolina, Columbia, SC, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dept. of Computer Science and Engineering, Univ. of South Carolina, Columbia, SC, USA","institution_ids":["https://openalex.org/I155781252"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5027937242","display_name":"Lothrop O. Richards","orcid":null},"institutions":[{"id":"https://openalex.org/I155781252","display_name":"University of South Carolina","ror":"https://ror.org/02b6qw903","country_code":"US","type":"education","lineage":["https://openalex.org/I155781252"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Lothrop O. Richards","raw_affiliation_strings":["Dept. of Computer Science and Engineering, Univ. of South Carolina, Columbia, SC, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dept. of Computer Science and Engineering, Univ. of South Carolina, Columbia, SC, USA","institution_ids":["https://openalex.org/I155781252"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5001266986","display_name":"Jason D. Bakos","orcid":"https://orcid.org/0000-0002-0821-6258"},"institutions":[{"id":"https://openalex.org/I155781252","display_name":"University of South Carolina","ror":"https://ror.org/02b6qw903","country_code":"US","type":"education","lineage":["https://openalex.org/I155781252"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jason D. Bakos","raw_affiliation_strings":["Dept. of Computer Science and Engineering, Univ. of South Carolina, Columbia, SC, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dept. of Computer Science and Engineering, Univ. of South Carolina, Columbia, SC, USA","institution_ids":["https://openalex.org/I155781252"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":2.3121,"has_fulltext":false,"cited_by_count":17,"citation_normalized_percentile":{"value":0.90384615,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"8"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12326","display_name":"Network Packet Processing and Optimization","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12326","display_name":"Network Packet Processing and Optimization","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9940999746322632,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9873999953269958,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8211997747421265},{"id":"https://openalex.org/keywords/arbiter","display_name":"Arbiter","score":0.6231861114501953},{"id":"https://openalex.org/keywords/overlay","display_name":"Overlay","score":0.5744560956954956},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.5036398768424988},{"id":"https://openalex.org/keywords/finite-state-machine","display_name":"Finite-state machine","score":0.4948205351829529},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4939029812812805},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.463159441947937},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4565652310848236},{"id":"https://openalex.org/keywords/automaton","display_name":"Automaton","score":0.4355413615703583},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.42620033025741577},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.16150224208831787},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.1603352427482605}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8211997747421265},{"id":"https://openalex.org/C2779971761","wikidata":"https://www.wikidata.org/wiki/Q629872","display_name":"Arbiter","level":2,"score":0.6231861114501953},{"id":"https://openalex.org/C136085584","wikidata":"https://www.wikidata.org/wiki/Q910289","display_name":"Overlay","level":2,"score":0.5744560956954956},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.5036398768424988},{"id":"https://openalex.org/C167822520","wikidata":"https://www.wikidata.org/wiki/Q176452","display_name":"Finite-state machine","level":2,"score":0.4948205351829529},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4939029812812805},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.463159441947937},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4565652310848236},{"id":"https://openalex.org/C112505250","wikidata":"https://www.wikidata.org/wiki/Q787116","display_name":"Automaton","level":2,"score":0.4355413615703583},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.42620033025741577},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.16150224208831787},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.1603352427482605},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/reconfig.2017.8279779","is_oa":false,"landing_page_url":"https://doi.org/10.1109/reconfig.2017.8279779","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 International Conference on ReConFigurable Computing and FPGAs (ReConFig)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5299999713897705,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W1521294226","https://openalex.org/W1707172707","https://openalex.org/W2030102079","https://openalex.org/W2040976214","https://openalex.org/W2044242345","https://openalex.org/W2046303323","https://openalex.org/W2062949766","https://openalex.org/W2067845746","https://openalex.org/W2122820686","https://openalex.org/W2139637699","https://openalex.org/W2170523504","https://openalex.org/W2218748714","https://openalex.org/W2236895266","https://openalex.org/W2241770856","https://openalex.org/W2323088261","https://openalex.org/W2335528805","https://openalex.org/W2529090470","https://openalex.org/W2530873820","https://openalex.org/W2728959903","https://openalex.org/W6637452973","https://openalex.org/W6680692090"],"related_works":["https://openalex.org/W2914607376","https://openalex.org/W2952166834","https://openalex.org/W4242459863","https://openalex.org/W127357700","https://openalex.org/W1480528870","https://openalex.org/W2508541108","https://openalex.org/W4243191745","https://openalex.org/W2724597727","https://openalex.org/W2315419748","https://openalex.org/W1029445510"],"abstract_inverted_index":{"This":[0,135],"paper":[1],"describes":[2],"a":[3,6,12,48,61,64,126,139,168],"design":[4,99,114,137],"for":[5,16,39,181],"parameterizable":[7],"automata":[8,45,67,205],"processor":[9,46,206],"overlay":[10,89,124],"and":[11,34,74,84,174,177],"placement":[13,183],"algorithm":[14,180],"required":[15],"its":[17],"support":[18],"software.":[19],"The":[20],"resulting":[21],"framework":[22,59],"serves":[23],"as":[24,35,164,193],"both":[25],"an":[26,36,92,103,179,203],"open-source":[27],"alternative":[28],"to":[29,52,79,117,147,167,186],"Micron's":[30,71],"Automata":[31],"Processor":[32],"(AP)":[33],"experimental":[37],"testbed":[38],"exploration":[40],"of":[41,63,87,102,105,119,158,202],"architectural":[42],"tradeoffs.":[43],"An":[44],"is":[47,100,115,198],"processor-in-memory":[49],"architecture":[50,163],"designed":[51],"recognize":[53],"patterns":[54],"in":[55,70,160],"streaming":[56],"data.":[57],"Our":[58],"takes":[60],"description":[62],"nondeterministic":[65],"finite":[66],"(NFA)":[68],"described":[69],"ANML":[72],"language":[73],"uses":[75,125],"instantiated":[76],"JTAG":[77],"sources":[78],"configure":[80],"the":[81,88,95,120,148,156,161,187,194,199],"on-chip":[82],"RAM":[83],"programmable":[85],"interconnect":[86,129,136,162],"programmed":[90],"onto":[91],"FPGA.":[93],"Like":[94],"Micron":[96,121],"AP,":[97,122],"our":[98,112,123],"comprised":[101],"array":[104],"interconnected":[106],"state":[107],"transition":[108],"elements":[109],"(STEs).":[110],"While":[111],"STE":[113,182],"equivalent":[116],"that":[118],"simpler,":[127],"non-switched":[128],"based":[130],"on":[131],"pairwise":[132],"gated":[133],"connections.":[134],"creates":[138],"constraint":[140],"satisfaction":[141],"problem":[142],"when":[143],"mapping":[144],"logical":[145],"states":[146],"physical":[149],"STEs.":[150],"In":[151],"this":[152,197],"paper,":[153],"we":[154,175],"explore":[155],"impact":[157],"tradeoffs":[159],"it":[165],"relates":[166],"Stratix":[169],"5":[170],"GX":[171],"target":[172],"device":[173],"describe":[176],"evaluate":[178],"with":[184],"respect":[185],"ANMLZoo":[188],"benchmark":[189],"suite.":[190],"As":[191],"far":[192],"authors":[195],"know,":[196],"first":[200],"example":[201],"FPGA-based":[204],"overlay.":[207]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":1},{"year":2020,"cited_by_count":4},{"year":2019,"cited_by_count":3},{"year":2018,"cited_by_count":3}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
