{"id":"https://openalex.org/W2787444967","doi":"https://doi.org/10.1109/reconfig.2017.8279771","title":"Accelerating low rank matrix completion on FPGA","display_name":"Accelerating low rank matrix completion on FPGA","publication_year":2017,"publication_date":"2017-12-01","ids":{"openalex":"https://openalex.org/W2787444967","doi":"https://doi.org/10.1109/reconfig.2017.8279771","mag":"2787444967"},"language":"en","primary_location":{"id":"doi:10.1109/reconfig.2017.8279771","is_oa":false,"landing_page_url":"https://doi.org/10.1109/reconfig.2017.8279771","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 International Conference on ReConFigurable Computing and FPGAs (ReConFig)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101624782","display_name":"Shijie Zhou","orcid":"https://orcid.org/0000-0002-9677-9594"},"institutions":[{"id":"https://openalex.org/I1174212","display_name":"University of Southern California","ror":"https://ror.org/03taz7m60","country_code":"US","type":"education","lineage":["https://openalex.org/I1174212"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Shijie Zhou","raw_affiliation_strings":["University of Southern California, Los Angeles, CA"],"affiliations":[{"raw_affiliation_string":"University of Southern California, Los Angeles, CA","institution_ids":["https://openalex.org/I1174212"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5042560222","display_name":"Rajgopal Kannan","orcid":"https://orcid.org/0000-0001-8736-3012"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Rajgopal Kannan","raw_affiliation_strings":["US Army Research Lab, Los Angeles, CA"],"affiliations":[{"raw_affiliation_string":"US Army Research Lab, Los Angeles, CA","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5033166029","display_name":"Viktor K. Prasanna","orcid":"https://orcid.org/0000-0002-1609-8589"},"institutions":[{"id":"https://openalex.org/I1174212","display_name":"University of Southern California","ror":"https://ror.org/03taz7m60","country_code":"US","type":"education","lineage":["https://openalex.org/I1174212"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Viktor K. Prasanna","raw_affiliation_strings":["University of Southern California, Los Angeles, CA"],"affiliations":[{"raw_affiliation_string":"University of Southern California, Los Angeles, CA","institution_ids":["https://openalex.org/I1174212"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5101624782"],"corresponding_institution_ids":["https://openalex.org/I1174212"],"apc_list":null,"apc_paid":null,"fwci":0.4802,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.65283257,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":91,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"7"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10500","display_name":"Sparse and Compressive Sensing Techniques","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/2206","display_name":"Computational Mechanics"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10500","display_name":"Sparse and Compressive Sensing Techniques","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/2206","display_name":"Computational Mechanics"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11612","display_name":"Stochastic Gradient Optimization Techniques","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9966999888420105,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.843864917755127},{"id":"https://openalex.org/keywords/pipeline","display_name":"Pipeline (software)","score":0.7042396068572998},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6310140490531921},{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.533211350440979},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.4535951018333435},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.448127418756485},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.34922102093696594},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.326651394367218}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.843864917755127},{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.7042396068572998},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6310140490531921},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.533211350440979},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.4535951018333435},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.448127418756485},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.34922102093696594},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.326651394367218},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/reconfig.2017.8279771","is_oa":false,"landing_page_url":"https://doi.org/10.1109/reconfig.2017.8279771","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 International Conference on ReConFigurable Computing and FPGAs (ReConFig)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":38,"referenced_works":["https://openalex.org/W1540248841","https://openalex.org/W1910302617","https://openalex.org/W1974811277","https://openalex.org/W1981868151","https://openalex.org/W2000157792","https://openalex.org/W2012408460","https://openalex.org/W2047071281","https://openalex.org/W2054141820","https://openalex.org/W2058162908","https://openalex.org/W2062140606","https://openalex.org/W2076246374","https://openalex.org/W2078815901","https://openalex.org/W2086465551","https://openalex.org/W2093994565","https://openalex.org/W2106005123","https://openalex.org/W2119697285","https://openalex.org/W2138835141","https://openalex.org/W2144730813","https://openalex.org/W2168231600","https://openalex.org/W2287057303","https://openalex.org/W2297086932","https://openalex.org/W2341535507","https://openalex.org/W2508029414","https://openalex.org/W2512527800","https://openalex.org/W2524937385","https://openalex.org/W2565305208","https://openalex.org/W2566870951","https://openalex.org/W2576259597","https://openalex.org/W2611328865","https://openalex.org/W2751366252","https://openalex.org/W2763806130","https://openalex.org/W2786845740","https://openalex.org/W3104393472","https://openalex.org/W4241140669","https://openalex.org/W4249932213","https://openalex.org/W6684859321","https://openalex.org/W6727261711","https://openalex.org/W6732355898"],"related_works":["https://openalex.org/W2058965144","https://openalex.org/W2164382479","https://openalex.org/W2146343568","https://openalex.org/W98480971","https://openalex.org/W2150291671","https://openalex.org/W2013643406","https://openalex.org/W2027972911","https://openalex.org/W2157978810","https://openalex.org/W4313341326","https://openalex.org/W4390693267"],"abstract_inverted_index":{"Low":[0],"Rank":[1],"Matrix":[2],"Completion":[3],"(LRMC)":[4],"is":[5,36,281],"widely":[6],"used":[7],"in":[8,200,255],"the":[9,64,85,118,140,161,180,201,237,246,265,289,294,301,312],"analysis":[10],"of":[11,63,157,160,170,204,248],"incomplete":[12],"datasets.":[13],"In":[14],"this":[15],"paper,":[16],"we":[17],"propose":[18,52,184],"a":[19,25,37,47,60,185,227],"novel":[20],"FPGA-based":[21],"accelerator":[22,35],"to":[23,117,214,270,284],"speedup":[24],"matrix-factorization-based":[26],"LRMC":[27],"algorithm":[28],"that":[29,196],"uses":[30],"stochastic":[31],"gradient":[32],"descent.":[33],"The":[34,122,250,278],"multi-pipelined":[38],"architecture":[39],"with":[40,274,293],"parallel":[41,129,219],"pipelines":[42],"processing":[43,98,169,179],"distinct":[44,54],"data":[45,216,251,260],"from":[46],"shared":[48],"on-chip":[49,55,93,106,148,202],"buffer.":[50],"We":[51,183,206,222,232],"two":[53,69,166,242],"buffer":[56,86],"architectures":[57],"based":[58,211],"on":[59,212,226],"design-space":[61],"exploration":[62],"performance":[65],"tradeoffs":[66],"offered":[67],"by":[68,138,244,268],"competing":[70],"design":[71,80,124,152,165,280,303,314],"methodologies:":[72],"memory-efficiency":[73],"versus":[74],"concurrent":[75,115],"conflict-free":[76],"accesses.":[77],"Our":[78],"first":[79],"(i.e.,":[81,125],"memory-efficient":[82,279,313],"design)":[83,127],"organizes":[84],"into":[87],"banks":[88],"and":[89,133,239,263,298,307,318],"maximally":[90],"utilizes":[91],"available":[92],"memory":[94,131,203],"for":[95,105,178,191,218,236],"matrix":[96,163,172],"chunk":[97],"without":[99],"requiring":[100],"complex":[101],"address":[102],"translation":[103],"tables":[104],"addressing;":[107],"however,":[108,143],"it":[109,144],"could":[110],"incur":[111],"bank":[112,120,136],"conflicts":[113,137],"when":[114],"accesses":[116],"same":[119],"occur.":[121],"second":[123],"bank-conflict-free":[126,290,302],"exploits":[128],"multiport":[130],"access":[132],"completely":[134],"eliminates":[135],"duplicating":[139],"stored":[141],"data;":[142],"has":[145],"much":[146],"higher":[147],"RAM":[149],"consumption.":[150],"Intuitively,":[151],"one":[153],"enables":[154,167],"(slower)":[155],"acceleration":[156],"(larger)":[158],"chunks":[159,173],"input":[162,194],"whereas":[164],"(faster)":[168],"(smaller)":[171],"but":[174,187],"requires":[175],"more":[176,286],"iterations":[177],"complete":[181],"matrix.":[182],"simple":[186],"efficient":[188],"partitioning":[189],"approach":[190],"supporting":[192],"large":[193],"matrices":[195],"do":[197],"not":[198],"fit":[199],"FPGA.":[205],"also":[207,282],"develop":[208],"algorithmic":[209],"optimizations":[210],"matching":[213],"reduce":[215],"dependencies":[217],"pipeline":[220],"execution.":[221],"implement":[223],"our":[224],"designs":[225,243],"state-of-the-art":[228,295],"UltraScale+":[229],"FPGA":[230],"device.":[231],"use":[233],"real-life":[234],"datasets":[235],"evaluation":[238],"compare":[240],"these":[241],"varying":[245],"number":[247],"pipelines.":[249],"dependency":[252,261],"optimization":[253],"results":[254],"at":[256],"least":[257],"21.6":[258],"x":[259,272,306,309,317,320],"reduction":[262],"improves":[264],"execution":[266],"time":[267],"up":[269],"66.3":[271],"compared":[273],"non-optimized":[275],"baseline":[276],"designs.":[277],"shown":[283],"be":[285],"scalable":[287],"than":[288],"design.":[291],"Compared":[292],"multi-core":[296],"implementation":[297],"GPU":[299],"implementation,":[300],"achieves":[304,315],"5.4":[305],"5.2":[308],"speedup,":[310,321],"respectively;":[311],"16.7":[316],"16.2":[319],"respectively.":[322]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
