{"id":"https://openalex.org/W2588631801","doi":"https://doi.org/10.1109/reconfig.2016.7857185","title":"ReOrder: Runtime datapath generation for high-throughput multi-stream processing","display_name":"ReOrder: Runtime datapath generation for high-throughput multi-stream processing","publication_year":2016,"publication_date":"2016-11-01","ids":{"openalex":"https://openalex.org/W2588631801","doi":"https://doi.org/10.1109/reconfig.2016.7857185","mag":"2588631801"},"language":"en","primary_location":{"id":"doi:10.1109/reconfig.2016.7857185","is_oa":false,"landing_page_url":"https://doi.org/10.1109/reconfig.2016.7857185","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 International Conference on ReConFigurable Computing and FPGAs (ReConFig)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5054355703","display_name":"Andreas Becher","orcid":"https://orcid.org/0000-0003-2750-7349"},"institutions":[{"id":"https://openalex.org/I181369854","display_name":"Friedrich-Alexander-Universit\u00e4t Erlangen-N\u00fcrnberg","ror":"https://ror.org/00f7hpc57","country_code":"DE","type":"education","lineage":["https://openalex.org/I181369854"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Andreas Becher","raw_affiliation_strings":["Department of Computer Science 12, Friedrich-Alexander-Universit\u00e4t Erlangen-N\u00fcrnberg (FAU), Germany"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science 12, Friedrich-Alexander-Universit\u00e4t Erlangen-N\u00fcrnberg (FAU), Germany","institution_ids":["https://openalex.org/I181369854"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5036056755","display_name":"Stefan Wildermann","orcid":"https://orcid.org/0000-0002-4324-2187"},"institutions":[{"id":"https://openalex.org/I181369854","display_name":"Friedrich-Alexander-Universit\u00e4t Erlangen-N\u00fcrnberg","ror":"https://ror.org/00f7hpc57","country_code":"DE","type":"education","lineage":["https://openalex.org/I181369854"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Stefan Wildermann","raw_affiliation_strings":["Department of Computer Science 12, Friedrich-Alexander-Universit\u00e4t Erlangen-N\u00fcrnberg (FAU), Germany"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science 12, Friedrich-Alexander-Universit\u00e4t Erlangen-N\u00fcrnberg (FAU), Germany","institution_ids":["https://openalex.org/I181369854"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5075980018","display_name":"Moritz M\u00fchlenthaler","orcid":"https://orcid.org/0000-0002-2729-127X"},"institutions":[{"id":"https://openalex.org/I181369854","display_name":"Friedrich-Alexander-Universit\u00e4t Erlangen-N\u00fcrnberg","ror":"https://ror.org/00f7hpc57","country_code":"DE","type":"education","lineage":["https://openalex.org/I181369854"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Moritz Muhlenthaler","raw_affiliation_strings":["Friedrich-Alexander-Universitat Erlangen-Nurnberg, Erlangen, Bayern, DE"],"affiliations":[{"raw_affiliation_string":"Friedrich-Alexander-Universitat Erlangen-Nurnberg, Erlangen, Bayern, DE","institution_ids":["https://openalex.org/I181369854"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5076672029","display_name":"J\u00fcrgen Teich","orcid":"https://orcid.org/0000-0001-6285-5862"},"institutions":[{"id":"https://openalex.org/I181369854","display_name":"Friedrich-Alexander-Universit\u00e4t Erlangen-N\u00fcrnberg","ror":"https://ror.org/00f7hpc57","country_code":"DE","type":"education","lineage":["https://openalex.org/I181369854"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Jurgen Teich","raw_affiliation_strings":["Department of Computer Science 12, Friedrich-Alexander-Universit\u00e4t Erlangen-N\u00fcrnberg (FAU), Germany"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science 12, Friedrich-Alexander-Universit\u00e4t Erlangen-N\u00fcrnberg (FAU), Germany","institution_ids":["https://openalex.org/I181369854"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5054355703"],"corresponding_institution_ids":["https://openalex.org/I181369854"],"apc_list":null,"apc_paid":null,"fwci":0.321,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.62792184,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":95},"biblio":{"volume":"56","issue":null,"first_page":"1","last_page":"8"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12326","display_name":"Network Packet Processing and Optimization","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/datapath","display_name":"Datapath","score":0.9076361656188965},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8215492963790894},{"id":"https://openalex.org/keywords/reconfigurability","display_name":"Reconfigurability","score":0.7839925289154053},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7524034976959229},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.6375067234039307},{"id":"https://openalex.org/keywords/hardware-acceleration","display_name":"Hardware acceleration","score":0.5731542110443115},{"id":"https://openalex.org/keywords/stream-processing","display_name":"Stream processing","score":0.527561604976654},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4936138391494751},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.46135637164115906},{"id":"https://openalex.org/keywords/host","display_name":"Host (biology)","score":0.4414348006248474},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3670012950897217},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3563762307167053},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.12889915704727173}],"concepts":[{"id":"https://openalex.org/C2781198647","wikidata":"https://www.wikidata.org/wiki/Q1633673","display_name":"Datapath","level":2,"score":0.9076361656188965},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8215492963790894},{"id":"https://openalex.org/C2780149590","wikidata":"https://www.wikidata.org/wiki/Q7302742","display_name":"Reconfigurability","level":2,"score":0.7839925289154053},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7524034976959229},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.6375067234039307},{"id":"https://openalex.org/C13164978","wikidata":"https://www.wikidata.org/wiki/Q600158","display_name":"Hardware acceleration","level":3,"score":0.5731542110443115},{"id":"https://openalex.org/C107027933","wikidata":"https://www.wikidata.org/wiki/Q2006448","display_name":"Stream processing","level":2,"score":0.527561604976654},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4936138391494751},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.46135637164115906},{"id":"https://openalex.org/C126831891","wikidata":"https://www.wikidata.org/wiki/Q221673","display_name":"Host (biology)","level":2,"score":0.4414348006248474},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3670012950897217},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3563762307167053},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.12889915704727173},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C18903297","wikidata":"https://www.wikidata.org/wiki/Q7150","display_name":"Ecology","level":1,"score":0.0},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/reconfig.2016.7857185","is_oa":false,"landing_page_url":"https://doi.org/10.1109/reconfig.2016.7857185","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 International Conference on ReConFigurable Computing and FPGAs (ReConFig)","raw_type":"proceedings-article"},{"id":"mag:2742830552","is_oa":false,"landing_page_url":"http://jglobal.jst.go.jp/en/public/20090422/201702242715703584","pdf_url":null,"source":{"id":"https://openalex.org/S4306512817","display_name":"IEEE Conference Proceedings","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":null,"raw_source_name":"IEEE Conference Proceedings","raw_type":null}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W1520485321","https://openalex.org/W1647595406","https://openalex.org/W1791587242","https://openalex.org/W1994493549","https://openalex.org/W2094224753","https://openalex.org/W2108166792","https://openalex.org/W2125703639","https://openalex.org/W2131595909","https://openalex.org/W2133138160","https://openalex.org/W2143909327","https://openalex.org/W2169957916","https://openalex.org/W2188922879","https://openalex.org/W2276268482","https://openalex.org/W2512638702","https://openalex.org/W3138367763","https://openalex.org/W3145158195","https://openalex.org/W6637101216","https://openalex.org/W6638231387"],"related_works":["https://openalex.org/W1544665014","https://openalex.org/W2748364266","https://openalex.org/W4243861219","https://openalex.org/W2159103767","https://openalex.org/W2121367602","https://openalex.org/W2537803004","https://openalex.org/W2518118925","https://openalex.org/W4285429137","https://openalex.org/W4293243607","https://openalex.org/W3159273459"],"abstract_inverted_index":{"Modern":[0],"Programmable":[1],"FPGA-based":[2],"SoCs":[3],"that":[4,54,177],"tightly":[5],"couple":[6],"CPU":[7],"and":[8,28,31,37,46,67,74,81,117,173],"programmable":[9,75],"logic":[10],"enable":[11],"the":[12,24,32,44,89,111,130,135,142,187,198],"acceleration":[13],"of":[14,23,48,63,88,115,137,186,197],"stream":[15,84,196],"processing":[16,85],"in":[17,35,127,134,159],"hardware":[18,50],"on-demand":[19],"by":[20],"making":[21],"use":[22],"available":[25],"high":[26,98],"input":[27,116],"output":[29,118],"throughputs":[30],"reconfigurability":[33],"both":[34],"software":[36],"hardware.":[38],"In":[39,93],"this":[40],"paper,":[41],"we":[42],"present":[43],"concept":[45],"implementation":[47],"a":[49,57,97],"unit":[51],"called":[52],"ReOrder":[53],"serves":[55],"as":[56],"converter":[58],"for":[59],"multiple":[60],"parallel":[61],"streams":[62],"data":[64,79,91,131,184,195],"read":[65],"from":[66],"written":[68],"to":[69,95,104,110,161,180,191],"an":[70,106,124,149,163,169],"accelerator.":[71],"Our":[72],"technique":[73],"design":[76,176],"allows":[77],"flexible":[78],"access":[80],"connects":[82],"different":[83],"accelerators":[86],"independent":[87],"host":[90,189],"layout.":[92],"order":[94,160],"achieve":[96],"accelerator":[99,143,199],"throughput,":[100],"it":[101],"is":[102,151,178],"necessary":[103],"determine":[105],"optimized":[107,164],"datapath":[108,165],"according":[109],"accelerator's":[112],"internal":[113],"schedule":[114],"data.":[119],"We":[120,167],"are":[121],"concerned":[122],"with":[123],"online":[125],"setting,":[126],"which":[128,153],"either":[129],"layout":[132],"(e.g.,":[133],"case":[136],"modern":[138],"database":[139],"systems)":[140],"or":[141],"operational":[144],"mode":[145],"change":[146],"dynamically.":[147],"Therefore,":[148],"algorithm":[150,172],"required":[152],"can":[154],"be":[155],"used":[156],"at":[157,200],"\u201cruntime\u201d":[158],"maintain":[162],"configuration.":[166],"propose":[168],"efficient":[170],"heuristic":[171],"corresponding":[174],"FPGA":[175],"able":[179],"translate":[181],"arbitrary":[182],"(multi-source)":[183],"layouts":[185],"connected":[188],"system":[190],"generate":[192],"any":[193],"specified":[194],"runtime":[201],"within":[202],"ms.":[203]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2018,"cited_by_count":1}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}