{"id":"https://openalex.org/W2587774835","doi":"https://doi.org/10.1109/reconfig.2016.7857147","title":"A scalable latency-insensitive architecture for FPGA-accelerated semi-global matching in stereo vision applications","display_name":"A scalable latency-insensitive architecture for FPGA-accelerated semi-global matching in stereo vision applications","publication_year":2016,"publication_date":"2016-11-01","ids":{"openalex":"https://openalex.org/W2587774835","doi":"https://doi.org/10.1109/reconfig.2016.7857147","mag":"2587774835"},"language":"en","primary_location":{"id":"doi:10.1109/reconfig.2016.7857147","is_oa":false,"landing_page_url":"https://doi.org/10.1109/reconfig.2016.7857147","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 International Conference on ReConFigurable Computing and FPGAs (ReConFig)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5088361257","display_name":"Jaco Hofmann","orcid":"https://orcid.org/0000-0003-3691-3293"},"institutions":[{"id":"https://openalex.org/I31512782","display_name":"Technical University of Darmstadt","ror":"https://ror.org/05n911h24","country_code":"DE","type":"education","lineage":["https://openalex.org/I31512782"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Jaco Hofmann","raw_affiliation_strings":["Embedded Systems and Applications Group (ESA), Technische Universit\u00e4t, Darmstadt, Germany"],"affiliations":[{"raw_affiliation_string":"Embedded Systems and Applications Group (ESA), Technische Universit\u00e4t, Darmstadt, Germany","institution_ids":["https://openalex.org/I31512782"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5031766879","display_name":"Jens Korinth","orcid":"https://orcid.org/0000-0002-5792-2562"},"institutions":[{"id":"https://openalex.org/I31512782","display_name":"Technical University of Darmstadt","ror":"https://ror.org/05n911h24","country_code":"DE","type":"education","lineage":["https://openalex.org/I31512782"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Jens Korinth","raw_affiliation_strings":["Embedded Systems and Applications Group (ESA), Technische Universit\u00e4t, Darmstadt, Germany"],"affiliations":[{"raw_affiliation_string":"Embedded Systems and Applications Group (ESA), Technische Universit\u00e4t, Darmstadt, Germany","institution_ids":["https://openalex.org/I31512782"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5047000315","display_name":"Andreas Koch","orcid":"https://orcid.org/0000-0002-1164-3082"},"institutions":[{"id":"https://openalex.org/I31512782","display_name":"Technical University of Darmstadt","ror":"https://ror.org/05n911h24","country_code":"DE","type":"education","lineage":["https://openalex.org/I31512782"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Andreas Koch","raw_affiliation_strings":["Embedded Systems and Applications Group (ESA), Technische Universit\u00e4t, Darmstadt, Germany"],"affiliations":[{"raw_affiliation_string":"Embedded Systems and Applications Group (ESA), Technische Universit\u00e4t, Darmstadt, Germany","institution_ids":["https://openalex.org/I31512782"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5088361257"],"corresponding_institution_ids":["https://openalex.org/I31512782"],"apc_list":null,"apc_paid":null,"fwci":0.501,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.74596808,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"8"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10531","display_name":"Advanced Vision and Imaging","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10531","display_name":"Advanced Vision and Imaging","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10191","display_name":"Robotics and Sensor-Based Localization","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2202","display_name":"Aerospace Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8115272521972656},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7381803393363953},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.6140530109405518},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.560232937335968},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.546777606010437},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.52791428565979},{"id":"https://openalex.org/keywords/low-latency","display_name":"Low latency (capital markets)","score":0.49855637550354004},{"id":"https://openalex.org/keywords/hardware-acceleration","display_name":"Hardware acceleration","score":0.48654332756996155},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.4547417163848877},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.43068018555641174},{"id":"https://openalex.org/keywords/stereopsis","display_name":"Stereopsis","score":0.4130380153656006},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3932070732116699},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.23894274234771729}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8115272521972656},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7381803393363953},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.6140530109405518},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.560232937335968},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.546777606010437},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.52791428565979},{"id":"https://openalex.org/C46637626","wikidata":"https://www.wikidata.org/wiki/Q6693015","display_name":"Low latency (capital markets)","level":2,"score":0.49855637550354004},{"id":"https://openalex.org/C13164978","wikidata":"https://www.wikidata.org/wiki/Q600158","display_name":"Hardware acceleration","level":3,"score":0.48654332756996155},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.4547417163848877},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.43068018555641174},{"id":"https://openalex.org/C68537008","wikidata":"https://www.wikidata.org/wiki/Q247932","display_name":"Stereopsis","level":2,"score":0.4130380153656006},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3932070732116699},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.23894274234771729},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/reconfig.2016.7857147","is_oa":false,"landing_page_url":"https://doi.org/10.1109/reconfig.2016.7857147","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 International Conference on ReConFigurable Computing and FPGAs (ReConFig)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.41999998688697815}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W1557905688","https://openalex.org/W1674866864","https://openalex.org/W1989291440","https://openalex.org/W2003173418","https://openalex.org/W2008399778","https://openalex.org/W2039175521","https://openalex.org/W2039548306","https://openalex.org/W2060799924","https://openalex.org/W2062272421","https://openalex.org/W2104974755","https://openalex.org/W2117248802","https://openalex.org/W2140836349","https://openalex.org/W2150066425","https://openalex.org/W2155479981","https://openalex.org/W2165114467","https://openalex.org/W2464066281","https://openalex.org/W4210960428","https://openalex.org/W6660188515","https://openalex.org/W6719240916"],"related_works":["https://openalex.org/W3133116121","https://openalex.org/W2625058759","https://openalex.org/W3115530580","https://openalex.org/W3195471267","https://openalex.org/W2148031998","https://openalex.org/W2622392763","https://openalex.org/W2971009090","https://openalex.org/W3032310658","https://openalex.org/W3193212547","https://openalex.org/W2390254310"],"abstract_inverted_index":{"Semi-Global":[0],"Matching":[1],"(SGM)":[2],"is":[3,21],"a":[4,37,57],"high-performance":[5],"method":[6],"for":[7,24],"computing":[8],"high-quality":[9],"disparity":[10],"maps":[11],"from":[12,43,63],"stereo":[13],"camera":[14],"images":[15],"in":[16,29],"machine":[17],"vision":[18],"applications.":[19],"It":[20],"also":[22],"suitable":[23],"direct":[25],"hardware":[26,68,105],"execution,":[27],"e.g.,":[28],"ASICs":[30],"or":[31],"reconfigurable":[32],"logic":[33],"devices.":[34],"We":[35],"present":[36],"highly":[38],"parametrized":[39],"FPGA":[40],"implementation,":[41],"scalable":[42],"simple":[44],"low-resolution":[45],"low-power":[46],"use-cases,":[47],"up":[48],"to":[49,103],"complex":[50],"real-time":[51],"full-HD":[52],"multi-camera":[53],"scenarios.":[54],"By":[55],"using":[56],"latency-insensitive":[58],"design":[59],"style,":[60],"high-level":[61],"synthesis":[62],"the":[64,89,96,100],"Bluespec":[65],"SystemVerilog":[66],"next-generation":[67],"description":[69],"language,":[70],"and":[71],"an":[72],"automated":[73],"design-space":[74],"exploration":[75],"flow,":[76],"many":[77],"implementation":[78],"alternatives":[79],"could":[80],"be":[81],"examined":[82],"with":[83],"high":[84],"productivity.":[85],"The":[86,107],"use":[87],"of":[88,99,112],"Threadpool":[90],"Composer":[91],"system-on-chip":[92],"assembly":[93],"tool":[94],"allows":[95],"portable":[97],"mapping":[98],"SGM":[101],"accelerator":[102,108],"different":[104],"platforms.":[106],"performance":[109],"exceeds":[110],"that":[111],"prior":[113],"fixed-architecture":[114],"approaches.":[115]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}