{"id":"https://openalex.org/W2281941492","doi":"https://doi.org/10.1109/reconfig.2015.7393356","title":"Scalable analytic placement for FPGA on GPGPU","display_name":"Scalable analytic placement for FPGA on GPGPU","publication_year":2015,"publication_date":"2015-12-01","ids":{"openalex":"https://openalex.org/W2281941492","doi":"https://doi.org/10.1109/reconfig.2015.7393356","mag":"2281941492"},"language":"en","primary_location":{"id":"doi:10.1109/reconfig.2015.7393356","is_oa":false,"landing_page_url":"https://doi.org/10.1109/reconfig.2015.7393356","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5020371776","display_name":"Ryan Pattison","orcid":null},"institutions":[{"id":"https://openalex.org/I79817857","display_name":"University of Guelph","ror":"https://ror.org/01r7awg59","country_code":"CA","type":"education","lineage":["https://openalex.org/I79817857"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"Ryan Pattison","raw_affiliation_strings":["School of Computer Science, University of Guelph, Ontario, Canada"],"affiliations":[{"raw_affiliation_string":"School of Computer Science, University of Guelph, Ontario, Canada","institution_ids":["https://openalex.org/I79817857"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5059685792","display_name":"Christian Fobel","orcid":"https://orcid.org/0000-0001-7602-4699"},"institutions":[{"id":"https://openalex.org/I79817857","display_name":"University of Guelph","ror":"https://ror.org/01r7awg59","country_code":"CA","type":"education","lineage":["https://openalex.org/I79817857"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Christian Fobel","raw_affiliation_strings":["School of Computer Science, University of Guelph, Ontario, Canada"],"affiliations":[{"raw_affiliation_string":"School of Computer Science, University of Guelph, Ontario, Canada","institution_ids":["https://openalex.org/I79817857"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5068888605","display_name":"Gary Gr\u00e9wal","orcid":"https://orcid.org/0000-0003-0845-6929"},"institutions":[{"id":"https://openalex.org/I79817857","display_name":"University of Guelph","ror":"https://ror.org/01r7awg59","country_code":"CA","type":"education","lineage":["https://openalex.org/I79817857"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Gary Grewal","raw_affiliation_strings":["School of Computer Science, University of Guelph, Ontario, Canada"],"affiliations":[{"raw_affiliation_string":"School of Computer Science, University of Guelph, Ontario, Canada","institution_ids":["https://openalex.org/I79817857"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5011873620","display_name":"Shawki Areibi","orcid":"https://orcid.org/0000-0003-4832-0911"},"institutions":[{"id":"https://openalex.org/I79817857","display_name":"University of Guelph","ror":"https://ror.org/01r7awg59","country_code":"CA","type":"education","lineage":["https://openalex.org/I79817857"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Shawki Areibi","raw_affiliation_strings":["School of Engineering, University of Guelph, Ontario, Canada"],"affiliations":[{"raw_affiliation_string":"School of Engineering, University of Guelph, Ontario, Canada","institution_ids":["https://openalex.org/I79817857"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5020371776"],"corresponding_institution_ids":["https://openalex.org/I79817857"],"apc_list":null,"apc_paid":null,"fwci":0.3946,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.6853295,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8288573026657104},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8194237947463989},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.7751958966255188},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.7210313081741333},{"id":"https://openalex.org/keywords/placement","display_name":"Placement","score":0.6952695250511169},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.5807510018348694},{"id":"https://openalex.org/keywords/critical-path-method","display_name":"Critical path method","score":0.5400022268295288},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.4210977256298065},{"id":"https://openalex.org/keywords/gate-array","display_name":"Gate array","score":0.4181826412677765},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.32163748145103455},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.21022093296051025},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.13519057631492615}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8288573026657104},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8194237947463989},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.7751958966255188},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.7210313081741333},{"id":"https://openalex.org/C117690923","wikidata":"https://www.wikidata.org/wiki/Q1484784","display_name":"Placement","level":4,"score":0.6952695250511169},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.5807510018348694},{"id":"https://openalex.org/C115874739","wikidata":"https://www.wikidata.org/wiki/Q825377","display_name":"Critical path method","level":2,"score":0.5400022268295288},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.4210977256298065},{"id":"https://openalex.org/C114237110","wikidata":"https://www.wikidata.org/wiki/Q114901","display_name":"Gate array","level":3,"score":0.4181826412677765},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.32163748145103455},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.21022093296051025},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.13519057631492615},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.0},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/reconfig.2015.7393356","is_oa":false,"landing_page_url":"https://doi.org/10.1109/reconfig.2015.7393356","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.550000011920929,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W1545099940","https://openalex.org/W1990050178","https://openalex.org/W1990649900","https://openalex.org/W2005602803","https://openalex.org/W2023461533","https://openalex.org/W2023462222","https://openalex.org/W2057839796","https://openalex.org/W2058324481","https://openalex.org/W2064997970","https://openalex.org/W2075137913","https://openalex.org/W2083838623","https://openalex.org/W2083862022","https://openalex.org/W2087977509","https://openalex.org/W2125290282","https://openalex.org/W2133898167","https://openalex.org/W2135063076","https://openalex.org/W2150871235","https://openalex.org/W2158961316","https://openalex.org/W4243050516"],"related_works":["https://openalex.org/W3146360095","https://openalex.org/W1571681534","https://openalex.org/W2184011203","https://openalex.org/W4399458808","https://openalex.org/W2042759115","https://openalex.org/W2367348190","https://openalex.org/W594316872","https://openalex.org/W113636695","https://openalex.org/W1980984060","https://openalex.org/W2110265185"],"abstract_inverted_index":{"The":[0,118,166,193],"growth":[1],"in":[2,11,80,187,206],"field-programmable":[3],"gate":[4],"array":[5],"(FPGA)":[6],"capacity":[7],"has":[8],"outpaced":[9],"improvements":[10],"serial":[12,150,164],"processor":[13],"speeds":[14],"for":[15,22,66],"the":[16,23,39,54,74,81,88,126,132,149,177],"last":[17],"decade":[18],"and":[19,35,58,69,136,155,182],"will":[20],"continue":[21,36],"foreseeable":[24],"future.":[25],"Unfortunately,":[26],"as":[27,131],"modern":[28],"FPGAs":[29],"have":[30,61],"millions":[31],"of":[32,41,56,138,148,158],"logic":[33],"elements":[34],"to":[37,49,162],"grow,":[38],"compilation":[40,76],"designs":[42],"can":[43],"take":[44],"hours":[45],"or":[46],"even":[47],"days":[48],"complete.":[50],"As":[51],"a":[52,63,98,105,145,203],"result,":[53],"runtimes":[55],"placement":[57,82,85,90,101,108,152],"routing":[59],"flow":[60],"become":[62],"major":[64],"concern":[65],"FPGA":[67,89,100],"users":[68],"vendors":[70],"alike.":[71],"Roughly":[72],"half":[73],"total":[75],"time":[77],"is":[78,122,144,170,195],"spent":[79],"phase.":[83],"Analytic":[84],"algorithms":[86],"solve":[87],"problem":[91,133],"quickly.":[92],"With":[93],"an":[94],"aim":[95],"toward":[96],"developing":[97],"scalable":[99],"algorithm,":[102],"we":[103],"present":[104],"parallel":[106,129,139,168],"analytic":[107,120,151],"algorithm":[109,143,153,169],"implemented":[110],"on":[111,171,196],"general-purpose":[112],"computing":[113],"graphics":[114],"processing":[115],"units":[116],"(GPGPUs).":[117],"proposed":[119,167],"placer":[121,127],"scalable,":[123],"that":[124],"is,":[125],"maintains":[128],"efficiency":[130],"size":[134],"grows":[135],"number":[137],"workers":[140],"increase.":[141],"Our":[142],"parallelized":[146],"version":[147],"StarPlace":[154],"achieves":[156],"speedups":[157],"13-31":[159],"times":[160,174],"compared":[161],"this":[163],"version.":[165],"average":[172,197],"78":[173],"faster":[175],"than":[176,200],"academic":[178],"tool":[179],"versatile":[180],"place":[181],"route":[183],"(VPR)":[184],"when":[185],"run":[186],"its":[188],"fast,":[189],"wirelength":[190,194],"driven":[191],"mode.":[192],"3%":[198],"lower":[199],"VPR,":[201],"with":[202],"24%":[204],"reduction":[205],"critical-path":[207],"delay.":[208]},"counts_by_year":[{"year":2024,"cited_by_count":2},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":2},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}