{"id":"https://openalex.org/W2282411511","doi":"https://doi.org/10.1109/reconfig.2015.7393352","title":"Towards a reconfigurable distributed testbed to enable advanced research and development of timing and synchronization in cyber-physical systems","display_name":"Towards a reconfigurable distributed testbed to enable advanced research and development of timing and synchronization in cyber-physical systems","publication_year":2015,"publication_date":"2015-12-01","ids":{"openalex":"https://openalex.org/W2282411511","doi":"https://doi.org/10.1109/reconfig.2015.7393352","mag":"2282411511"},"language":"en","primary_location":{"id":"doi:10.1109/reconfig.2015.7393352","is_oa":false,"landing_page_url":"https://doi.org/10.1109/reconfig.2015.7393352","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5052699654","display_name":"Hugo A. Andrade","orcid":"https://orcid.org/0000-0002-4560-8859"},"institutions":[{"id":"https://openalex.org/I4210124763","display_name":"National Instruments (United States)","ror":"https://ror.org/026exqw73","country_code":"US","type":"company","lineage":["https://openalex.org/I4210117810","https://openalex.org/I4210124763"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Hugo A. Andrade","raw_affiliation_strings":["National Instruments, Berkeley, CA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"National Instruments, Berkeley, CA","institution_ids":["https://openalex.org/I4210124763"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5056449142","display_name":"Patricia Derler","orcid":"https://orcid.org/0000-0001-7742-802X"},"institutions":[{"id":"https://openalex.org/I4210124763","display_name":"National Instruments (United States)","ror":"https://ror.org/026exqw73","country_code":"US","type":"company","lineage":["https://openalex.org/I4210117810","https://openalex.org/I4210124763"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Patricia Derler","raw_affiliation_strings":["National Instruments, Berkeley, CA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"National Instruments, Berkeley, CA","institution_ids":["https://openalex.org/I4210124763"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5076397754","display_name":"John C. Eidson","orcid":null},"institutions":[{"id":"https://openalex.org/I95457486","display_name":"University of California, Berkeley","ror":"https://ror.org/01an7q238","country_code":"US","type":"education","lineage":["https://openalex.org/I95457486"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"John C. Eidson","raw_affiliation_strings":["University of California, Berkeley"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of California, Berkeley","institution_ids":["https://openalex.org/I95457486"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5058440761","display_name":"Ya-Shian Li-Baboud","orcid":"https://orcid.org/0000-0003-3234-4345"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Ya-Shian Li-Baboud","raw_affiliation_strings":["NIST Software and Systems Division, Gaithersburg, MD"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"NIST Software and Systems Division, Gaithersburg, MD","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5044172378","display_name":"Aviral Shrivastava","orcid":"https://orcid.org/0000-0002-1075-897X"},"institutions":[{"id":"https://openalex.org/I55732556","display_name":"Arizona State University","ror":"https://ror.org/03efmqc40","country_code":"US","type":"education","lineage":["https://openalex.org/I55732556"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Aviral Shrivastava","raw_affiliation_strings":["Arizona State University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Arizona State University","institution_ids":["https://openalex.org/I55732556"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5050905663","display_name":"Kevin Stanton","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kevin Stanton","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5013633510","display_name":"Marc A. Weiss","orcid":"https://orcid.org/0000-0002-6521-2827"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Marc Weiss","raw_affiliation_strings":["NIST Time and Frequency Division, Boulder, CO"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"NIST Time and Frequency Division, Boulder, CO","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.2246,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.78468152,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11125","display_name":"Petri Nets in System Modeling","score":0.9959999918937683,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.782139778137207},{"id":"https://openalex.org/keywords/synchronization","display_name":"Synchronization (alternating current)","score":0.702161431312561},{"id":"https://openalex.org/keywords/testbed","display_name":"Testbed","score":0.6763251423835754},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5720993280410767},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5419356226921082},{"id":"https://openalex.org/keywords/cyber-physical-system","display_name":"Cyber-physical system","score":0.5406320691108704},{"id":"https://openalex.org/keywords/correctness","display_name":"Correctness","score":0.5244669914245605},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.5008642673492432},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.49708011746406555},{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.4649679958820343},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.3935222625732422},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.1743270754814148}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.782139778137207},{"id":"https://openalex.org/C2778562939","wikidata":"https://www.wikidata.org/wiki/Q1298791","display_name":"Synchronization (alternating current)","level":3,"score":0.702161431312561},{"id":"https://openalex.org/C31395832","wikidata":"https://www.wikidata.org/wiki/Q1318674","display_name":"Testbed","level":2,"score":0.6763251423835754},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5720993280410767},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5419356226921082},{"id":"https://openalex.org/C179768478","wikidata":"https://www.wikidata.org/wiki/Q1120057","display_name":"Cyber-physical system","level":2,"score":0.5406320691108704},{"id":"https://openalex.org/C55439883","wikidata":"https://www.wikidata.org/wiki/Q360812","display_name":"Correctness","level":2,"score":0.5244669914245605},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.5008642673492432},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.49708011746406555},{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.4649679958820343},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.3935222625732422},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.1743270754814148},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/reconfig.2015.7393352","is_oa":false,"landing_page_url":"https://doi.org/10.1109/reconfig.2015.7393352","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.6299999952316284,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W1488202922","https://openalex.org/W1556635491","https://openalex.org/W1967368511","https://openalex.org/W1994661703","https://openalex.org/W2071229589","https://openalex.org/W2169239645","https://openalex.org/W2288632536","https://openalex.org/W2309218921"],"related_works":["https://openalex.org/W2883256816","https://openalex.org/W2171408034","https://openalex.org/W3003320923","https://openalex.org/W2106140982","https://openalex.org/W2152313554","https://openalex.org/W3089038912","https://openalex.org/W3123953333","https://openalex.org/W2625101315","https://openalex.org/W2763653188","https://openalex.org/W2143442623"],"abstract_inverted_index":{"Timing":[0],"and":[1,29,51,62,75,80,115,138,146,162,171,178,204,207],"synchronization":[2,172],"play":[3],"a":[4,37,101,106,143,150],"key":[5],"role":[6],"in":[7,16,173,192],"cyber-physical":[8],"systems":[9,64],"(CPS).":[10],"Precise":[11],"timing,":[12],"as":[13,55,57,100,195],"often":[14],"required":[15],"safety-critical":[17],"CPS,":[18,34],"depends":[19],"on":[20],"hardware":[21],"support":[22,71,156,168],"for":[23,72,129,149,169,182],"enforcement":[24],"of":[25,39,68,117,132,160,197],"periodic":[26],"measure,":[27],"compute,":[28],"actuate":[30],"cycles.":[31],"For":[32],"general":[33],"designers":[35,92],"use":[36,147],"combination":[38],"application":[40,209],"specific":[41],"integrated":[42],"circuits":[43],"(ASICs)":[44],"or":[45,109,135],"field":[46],"programmable":[47],"gate":[48],"arrays":[49],"(FPGAs)":[50],"conventional":[52],"microprocessors.":[53],"Microprocessors":[54],"well":[56],"commonly":[58],"used":[59,90,188],"computer":[60,78],"languages":[61],"operating":[63],"are":[65,112],"essentially":[66],"devoid":[67],"any":[69],"explicit":[70,167],"precise":[73],"timing":[74],"synchronization.":[76],"Modern":[77],"science":[79],"microprocessor":[81],"design":[82,145,179],"has":[83],"effectively":[84],"removed":[85],"time":[86,97,170],"from":[87],"the":[88,94,124,190,198,202,208],"abstractions":[89],"by":[91],"with":[93],"result":[95],"that":[96],"is":[98,126,187],"regarded":[99],"performance":[102],"metric":[103],"rather":[104],"than":[105],"correctness":[107],"specification":[108],"criterion.":[110],"There":[111],"interesting":[113],"proposals":[114],"avenues":[116],"research":[118,137],"to":[119,155,165],"correct":[120],"this":[121],"situation,":[122],"but":[123],"barrier":[125],"quite":[127],"high":[128],"conducting":[130],"proof":[131,159],"concept":[133],"studies":[134],"collaborative":[136,163],"development.":[139],"This":[140],"paper":[141],"proposes":[142],"conceptual":[144],"model":[148],"reconfigurable":[151,175],"testbed":[152],"designed":[153],"specifically":[154],"exploratory":[157],"research,":[158],"concept,":[161],"work":[164],"introduce":[166],"microprocessors,":[174],"fabrics,":[176],"language":[177],"system":[180,191,210],"architecture":[181],"time-sensitive":[183],"CPS.":[184],"Reconfigurable":[185],"computing":[186],"throughout":[189],"several":[193],"roles:":[194],"part":[196],"prototyping":[199],"platform":[200],"infrastructure,":[201],"measurement":[203],"control":[205],"system,":[206],"under":[211],"test.":[212]},"counts_by_year":[{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":3}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}