{"id":"https://openalex.org/W2059059410","doi":"https://doi.org/10.1109/reconfig.2014.7032565","title":"What limits the operating frequency of a soft processor design","display_name":"What limits the operating frequency of a soft processor design","publication_year":2014,"publication_date":"2014-12-01","ids":{"openalex":"https://openalex.org/W2059059410","doi":"https://doi.org/10.1109/reconfig.2014.7032565","mag":"2059059410"},"language":"en","primary_location":{"id":"doi:10.1109/reconfig.2014.7032565","is_oa":false,"landing_page_url":"https://doi.org/10.1109/reconfig.2014.7032565","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5051051452","display_name":"Kaveh Aasaraai","orcid":null},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Kaveh Aasaraai","raw_affiliation_strings":["Electrical and Computer Engineering Department, University of Toronto, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering Department, University of Toronto, Canada","institution_ids":["https://openalex.org/I185261750"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5072544251","display_name":"Andreas Moshovos","orcid":"https://orcid.org/0000-0001-7768-367X"},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Andreas Moshovos","raw_affiliation_strings":["Electrical and Computer Engineering Department, University of Toronto, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering Department, University of Toronto, Canada","institution_ids":["https://openalex.org/I185261750"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I185261750"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.12914648,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7723240852355957},{"id":"https://openalex.org/keywords/correctness","display_name":"Correctness","score":0.7130159139633179},{"id":"https://openalex.org/keywords/stratix","display_name":"Stratix","score":0.6594057679176331},{"id":"https://openalex.org/keywords/processor-design","display_name":"Processor design","score":0.6393176913261414},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.6387195587158203},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6016907095909119},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.5267041325569153},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.446617990732193},{"id":"https://openalex.org/keywords/modularity","display_name":"Modularity (biology)","score":0.4239584803581238},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3964208960533142},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.38091886043548584},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.19098350405693054}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7723240852355957},{"id":"https://openalex.org/C55439883","wikidata":"https://www.wikidata.org/wiki/Q360812","display_name":"Correctness","level":2,"score":0.7130159139633179},{"id":"https://openalex.org/C2776277307","wikidata":"https://www.wikidata.org/wiki/Q22074755","display_name":"Stratix","level":3,"score":0.6594057679176331},{"id":"https://openalex.org/C526435321","wikidata":"https://www.wikidata.org/wiki/Q1303814","display_name":"Processor design","level":2,"score":0.6393176913261414},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.6387195587158203},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6016907095909119},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.5267041325569153},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.446617990732193},{"id":"https://openalex.org/C2779478453","wikidata":"https://www.wikidata.org/wiki/Q6889748","display_name":"Modularity (biology)","level":2,"score":0.4239584803581238},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3964208960533142},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.38091886043548584},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.19098350405693054},{"id":"https://openalex.org/C54355233","wikidata":"https://www.wikidata.org/wiki/Q7162","display_name":"Genetics","level":1,"score":0.0},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/reconfig.2014.7032565","is_oa":false,"landing_page_url":"https://doi.org/10.1109/reconfig.2014.7032565","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.7099999785423279,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W2016889342","https://openalex.org/W2043057288","https://openalex.org/W2122563027","https://openalex.org/W2154346069","https://openalex.org/W2157855196","https://openalex.org/W6678438195"],"related_works":["https://openalex.org/W1667647204","https://openalex.org/W2404647514","https://openalex.org/W2005778825","https://openalex.org/W2388165298","https://openalex.org/W2099626079","https://openalex.org/W2059059410","https://openalex.org/W2952180633","https://openalex.org/W3122690402","https://openalex.org/W137556601","https://openalex.org/W1599810211"],"abstract_inverted_index":{"This":[0],"work":[1,115],"systematically":[2],"explores":[3],"what":[4],"limits":[5],"the":[6,47,63,66,85,103,109,121,131],"operation":[7],"frequency":[8,86,134],"in":[9,54,99],"a":[10,18,24,31,35,55,77],"typical":[11,25],"general":[12],"purpose,":[13],"soft":[14],"processor":[15,132],"design":[16,26],"on":[17,139],"modern":[19],"FPGA.":[20],"The":[21,50,74,128],"analysis":[22,51,64],"mirrors":[23],"cycle:":[27],"It":[28],"starts":[29],"from":[30,135],"base":[32],"implementation":[33],"of":[34,44,57,79,87,111,123,125],"5-stage":[36],"pipelined":[37],"core":[38],"where":[39],"correctness,":[40],"modularity,":[41],"and":[42,69,81],"speed":[43],"development":[45],"are":[46],"primary":[48],"considerations.":[49],"then":[52,70],"proceeds":[53],"series":[56],"identify-and-then-revise":[58],"steps.":[59],"At":[60],"each":[61],"step,":[62],"identifies":[65],"critical":[67],"path":[68],"\"removes":[71],"\"":[72],"it.":[73],"result":[75],"is":[76],"list":[78],"components":[80],"mechanisms":[82],"that":[83],"restrict":[84],"operation.":[88],"A":[89],"designer":[90],"would":[91],"have":[92],"to":[93,101,119,137],"cleverly":[94],"redesign":[95],"over":[96],"these":[97,126],"paths":[98],"order":[100],"improve":[102,120],"processor's":[104],"operating":[105],"clock":[106,133],"frequency.":[107],"Using":[108],"results":[110],"this":[112,114],"analysis,":[113],"proposes":[116],"various":[117],"optimizations":[118,129],"efficiency":[122],"some":[124],"components.":[127],"increase":[130],"145MHz":[136],"281MHz":[138],"Stratix":[140],"III":[141],"devices,":[142],"while":[143],"overall":[144],"instruction":[145],"processing":[146],"throughput":[147],"increases":[148],"by":[149],"80%.":[150]},"counts_by_year":[{"year":2020,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}