{"id":"https://openalex.org/W1974461433","doi":"https://doi.org/10.1109/reconfig.2014.7032532","title":"Hardware/software infrastructure for ASIC commissioning and rapid system prototyping","display_name":"Hardware/software infrastructure for ASIC commissioning and rapid system prototyping","publication_year":2014,"publication_date":"2014-12-01","ids":{"openalex":"https://openalex.org/W1974461433","doi":"https://doi.org/10.1109/reconfig.2014.7032532","mag":"1974461433"},"language":"en","primary_location":{"id":"doi:10.1109/reconfig.2014.7032532","is_oa":false,"landing_page_url":"https://doi.org/10.1109/reconfig.2014.7032532","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"http://publica.fraunhofer.de/documents/N-336426.html","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5069006979","display_name":"Peter Reichel","orcid":"https://orcid.org/0000-0001-7149-8238"},"institutions":[{"id":"https://openalex.org/I4210095661","display_name":"Fraunhofer Institute for Integrated Circuits IIS, Division Engineering of Adaptive Systems EAS","ror":"https://ror.org/00s5yp124","country_code":"DE","type":"facility","lineage":["https://openalex.org/I4210095661","https://openalex.org/I4210124274","https://openalex.org/I4923324"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Peter Reichel","raw_affiliation_strings":["Fraunhofer Institute for Integrated Circuits IIS, Design Automation Division EAS, Zeunerstr. 38, 01069 Dresden, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Fraunhofer Institute for Integrated Circuits IIS, Design Automation Division EAS, Zeunerstr. 38, 01069 Dresden, Germany","institution_ids":["https://openalex.org/I4210095661"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5029436588","display_name":"Jens D\u00f6ge","orcid":"https://orcid.org/0000-0002-2891-984X"},"institutions":[{"id":"https://openalex.org/I4210095661","display_name":"Fraunhofer Institute for Integrated Circuits IIS, Division Engineering of Adaptive Systems EAS","ror":"https://ror.org/00s5yp124","country_code":"DE","type":"facility","lineage":["https://openalex.org/I4210095661","https://openalex.org/I4210124274","https://openalex.org/I4923324"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Jens Doge","raw_affiliation_strings":["Fraunhofer Institute for Integrated Circuits IIS, Design Automation Division EAS, Zeunerstr. 38, 01069 Dresden, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Fraunhofer Institute for Integrated Circuits IIS, Design Automation Division EAS, Zeunerstr. 38, 01069 Dresden, Germany","institution_ids":["https://openalex.org/I4210095661"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.3151,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.57105106,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"1","issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.7420012950897217},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6804084777832031},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.6587449312210083},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6419047713279724},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.5679485201835632},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.5566135048866272},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.5561147332191467},{"id":"https://openalex.org/keywords/fpga-prototype","display_name":"FPGA prototype","score":0.5106733441352844},{"id":"https://openalex.org/keywords/flexibility","display_name":"Flexibility (engineering)","score":0.5068002343177795},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.4740540683269501},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.42947331070899963},{"id":"https://openalex.org/keywords/kernel","display_name":"Kernel (algebra)","score":0.4146432876586914}],"concepts":[{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.7420012950897217},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6804084777832031},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.6587449312210083},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6419047713279724},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.5679485201835632},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.5566135048866272},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.5561147332191467},{"id":"https://openalex.org/C203864433","wikidata":"https://www.wikidata.org/wiki/Q5426992","display_name":"FPGA prototype","level":3,"score":0.5106733441352844},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.5068002343177795},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.4740540683269501},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.42947331070899963},{"id":"https://openalex.org/C74193536","wikidata":"https://www.wikidata.org/wiki/Q574844","display_name":"Kernel (algebra)","level":2,"score":0.4146432876586914},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/reconfig.2014.7032532","is_oa":false,"landing_page_url":"https://doi.org/10.1109/reconfig.2014.7032532","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14)","raw_type":"proceedings-article"},{"id":"pmh:oai:fraunhofer.de:N-336426","is_oa":true,"landing_page_url":"http://publica.fraunhofer.de/documents/N-336426.html","pdf_url":null,"source":{"id":"https://openalex.org/S4306400318","display_name":"Fraunhofer-Publica (Fraunhofer-Gesellschaft)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I4923324","host_organization_name":"Fraunhofer-Gesellschaft","host_organization_lineage":["https://openalex.org/I4923324"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Fraunhofer EAS","raw_type":"conferenceObject"},{"id":"pmh:oai:publica.fraunhofer.de:publica/387062","is_oa":false,"landing_page_url":"https://publica.fraunhofer.de/handle/publica/387062","pdf_url":null,"source":{"id":"https://openalex.org/S4306400318","display_name":"Fraunhofer-Publica (Fraunhofer-Gesellschaft)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I4923324","host_organization_name":"Fraunhofer-Gesellschaft","host_organization_lineage":["https://openalex.org/I4923324"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"conference paper"}],"best_oa_location":{"id":"pmh:oai:fraunhofer.de:N-336426","is_oa":true,"landing_page_url":"http://publica.fraunhofer.de/documents/N-336426.html","pdf_url":null,"source":{"id":"https://openalex.org/S4306400318","display_name":"Fraunhofer-Publica (Fraunhofer-Gesellschaft)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I4923324","host_organization_name":"Fraunhofer-Gesellschaft","host_organization_lineage":["https://openalex.org/I4923324"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Fraunhofer EAS","raw_type":"conferenceObject"},"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.6200000047683716}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W21101018","https://openalex.org/W1542986186","https://openalex.org/W1561321138","https://openalex.org/W1997470865","https://openalex.org/W2037320239","https://openalex.org/W2046964635","https://openalex.org/W2123495558","https://openalex.org/W2126948472","https://openalex.org/W2178394238","https://openalex.org/W2481725867","https://openalex.org/W4233037448","https://openalex.org/W4240187346","https://openalex.org/W4246084264","https://openalex.org/W4247806563","https://openalex.org/W4252622709","https://openalex.org/W4302068331","https://openalex.org/W6633668750"],"related_works":["https://openalex.org/W1485756991","https://openalex.org/W2998132311","https://openalex.org/W2207067480","https://openalex.org/W4383823603","https://openalex.org/W1692883217","https://openalex.org/W2406926880","https://openalex.org/W2332075903","https://openalex.org/W1579891439","https://openalex.org/W2376218453","https://openalex.org/W2984236338"],"abstract_inverted_index":{"FPGAs":[0],"are":[1,89],"a":[2,72,94,118],"key":[3],"enabling":[4],"technology":[5],"for":[6,99],"rapid":[7],"and":[8,12,26,36,57,120],"efficient":[9],"system":[10,97],"prototyping":[11],"initial":[13],"commissioning":[14],"of":[15,28,55,67],"newly":[16],"developed":[17],"integrated":[18],"circuits.":[19],"One":[20],"major":[21],"aspect":[22],"is":[23,102],"the":[24,37,49,68,139],"setup":[25],"control":[27],"interface":[29,84],"components":[30,85],"between":[31],"devices":[32],"under":[33],"test":[34],"(DUT)":[35],"FPGA":[38],"infrastructure.":[39,76],"So,":[40],"as":[41,60,62,80,91,104],"to":[42,51,86,93,111,129],"maintain":[43],"high":[44],"flexibility":[45],"in":[46],"conjunction":[47],"with":[48,53],"ability":[50],"deal":[52],"changes":[54],"requirements":[56],"use":[58],"cases,":[59],"well":[61],"unforeseen":[63],"or":[64,83],"faulty":[65],"behavior":[66],"DUT,":[69],"we":[70],"propose":[71],"novel":[73],"reconfigurable":[74],"hardware/software":[75,140],"IP":[77],"blocks,":[78],"such":[79],"register":[81],"files":[82],"external":[87],"hardware":[88],"attached":[90],"leafs":[92],"tree-like":[95],"communication":[96],"optimized":[98],"alterations.":[100],"It":[101],"designed":[103],"an":[105],"Embedded":[106],"Linux":[107],"compatible":[108],"CPU":[109],"subsystem":[110],"be":[112],"accessed":[113],"from":[114,132],"user":[115,133],"space":[116],"via":[117],"uniform":[119],"portable":[121],"kernel":[122],"driver.":[123],"Thus,":[124],"it":[125],"implements":[126],"transparent":[127],"access":[128],"custom":[130],"functionality":[131],"applications":[134],"without":[135],"specific":[136],"knowledge":[137],"concerning":[138],"coupling.":[141]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2016,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}