{"id":"https://openalex.org/W2021295531","doi":"https://doi.org/10.1109/reconfig.2014.7032505","title":"Characterization of OpenCL on a scalable FPGA architecture","display_name":"Characterization of OpenCL on a scalable FPGA architecture","publication_year":2014,"publication_date":"2014-12-01","ids":{"openalex":"https://openalex.org/W2021295531","doi":"https://doi.org/10.1109/reconfig.2014.7032505","mag":"2021295531"},"language":"en","primary_location":{"id":"doi:10.1109/reconfig.2014.7032505","is_oa":false,"landing_page_url":"https://doi.org/10.1109/reconfig.2014.7032505","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5046067082","display_name":"Shanyuan Gao","orcid":"https://orcid.org/0000-0001-7113-125X"},"institutions":[{"id":"https://openalex.org/I4210143490","display_name":"Computing Center","ror":"https://ror.org/0557kgc34","country_code":"RU","type":"facility","lineage":["https://openalex.org/I1313323035","https://openalex.org/I4210143490","https://openalex.org/I4210148470"]},{"id":"https://openalex.org/I4210153530","display_name":"Policy Innovation and Co-ordination Office","ror":"https://ror.org/052p8vb75","country_code":"HK","type":"government","lineage":["https://openalex.org/I2800550174","https://openalex.org/I4210153530"]}],"countries":["HK","RU"],"is_corresponding":false,"raw_author_name":"Shanyuan Gao","raw_affiliation_strings":["Pico Computing, Inc"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Pico Computing, Inc","institution_ids":["https://openalex.org/I4210143490","https://openalex.org/I4210153530"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5019932573","display_name":"Jeremy Chritz","orcid":null},"institutions":[{"id":"https://openalex.org/I4210143490","display_name":"Computing Center","ror":"https://ror.org/0557kgc34","country_code":"RU","type":"facility","lineage":["https://openalex.org/I1313323035","https://openalex.org/I4210143490","https://openalex.org/I4210148470"]},{"id":"https://openalex.org/I4210153530","display_name":"Policy Innovation and Co-ordination Office","ror":"https://ror.org/052p8vb75","country_code":"HK","type":"government","lineage":["https://openalex.org/I2800550174","https://openalex.org/I4210153530"]}],"countries":["HK","RU"],"is_corresponding":false,"raw_author_name":"Jeremy Chritz","raw_affiliation_strings":["Pico Computing, Inc"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Pico Computing, Inc","institution_ids":["https://openalex.org/I4210143490","https://openalex.org/I4210153530"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.6123,"has_fulltext":false,"cited_by_count":21,"citation_normalized_percentile":{"value":0.82277302,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.995199978351593,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9872000217437744,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/stratix","display_name":"Stratix","score":0.9004515409469604},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8881516456604004},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8393630981445312},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.7388118505477905},{"id":"https://openalex.org/keywords/modular-design","display_name":"Modular design","score":0.4916995167732239},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.48335903882980347},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.48047083616256714},{"id":"https://openalex.org/keywords/fpga-prototype","display_name":"FPGA prototype","score":0.479440838098526},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.47488516569137573},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.46462568640708923},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.41609370708465576},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.41271090507507324},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.32931697368621826},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3264588713645935},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.1459314525127411}],"concepts":[{"id":"https://openalex.org/C2776277307","wikidata":"https://www.wikidata.org/wiki/Q22074755","display_name":"Stratix","level":3,"score":0.9004515409469604},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8881516456604004},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8393630981445312},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.7388118505477905},{"id":"https://openalex.org/C101468663","wikidata":"https://www.wikidata.org/wiki/Q1620158","display_name":"Modular design","level":2,"score":0.4916995167732239},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.48335903882980347},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.48047083616256714},{"id":"https://openalex.org/C203864433","wikidata":"https://www.wikidata.org/wiki/Q5426992","display_name":"FPGA prototype","level":3,"score":0.479440838098526},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.47488516569137573},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.46462568640708923},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.41609370708465576},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.41271090507507324},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.32931697368621826},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3264588713645935},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.1459314525127411},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/reconfig.2014.7032505","is_oa":false,"landing_page_url":"https://doi.org/10.1109/reconfig.2014.7032505","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.49000000953674316}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W172049653","https://openalex.org/W1968432902","https://openalex.org/W2000921084","https://openalex.org/W2016357834","https://openalex.org/W2046607278","https://openalex.org/W2078555859","https://openalex.org/W2087054398","https://openalex.org/W2096525649","https://openalex.org/W2127699991","https://openalex.org/W2136084694","https://openalex.org/W2146496959","https://openalex.org/W2148466748","https://openalex.org/W2149234156","https://openalex.org/W2171429297","https://openalex.org/W2256201213","https://openalex.org/W2399715892","https://openalex.org/W6607026121"],"related_works":["https://openalex.org/W1509155667","https://openalex.org/W2518118925","https://openalex.org/W2113648965","https://openalex.org/W2155484023","https://openalex.org/W4200391368","https://openalex.org/W2388221044","https://openalex.org/W2984236338","https://openalex.org/W2619213283","https://openalex.org/W3117064361","https://openalex.org/W2057745131"],"abstract_inverted_index":{"The":[0,58,69,102,122,140,162,176],"recent":[1],"release":[2],"of":[3,13,34,72,78,110],"Altera's":[4,98],"SDK":[5],"for":[6,54,85,131,137],"OpenCL":[7,23,38,99,151],"has":[8,48,104],"greatly":[9],"eased":[10],"the":[11,32,76,106,111,114,158],"development":[12],"FPGA-based":[14],"systems.":[15],"Research":[16],"have":[17,116,165],"shown":[18,166],"performance":[19,36,56,67,109],"improvements":[20],"brought":[21],"by":[22],"using":[24,43,119,183],"a":[25,50,65,187],"single":[26],"FPGA":[27,52,62,89],"device.":[28],"However,":[29],"to":[30,40,156],"meet":[31],"objectives":[33],"high":[35,55,66],"computing,":[37],"needs":[39],"be":[41],"evaluated":[42],"multiple":[44,61],"FPGAs.":[45,121],"This":[46],"work":[47],"proposed":[49],"scalable":[51,159],"architecture":[53,74,112],"computing.":[57],"design":[59],"includes":[60],"modules":[63,90],"and":[64,113,134],"backplane.":[68],"modular":[70],"nature":[71],"this":[73],"supports":[75],"combination":[77],"different":[79],"FPGAs,":[80,185],"as":[81,83,128,145],"well":[82],"provides":[84],"easy":[86],"hardware":[87],"updates.":[88],"based":[91],"on":[92],"Stratix":[93],"V":[94],"are":[95,174],"compatible":[96],"with":[97],"tool":[100],"flow.":[101],"evaluation":[103],"tested":[105],"native":[107],"IO":[108],"results":[115,164],"demonstrated":[117],"scalability":[118],"six":[120,172],"host-to-device":[123],"peak":[124,167],"bandwidth":[125,142],"is":[126,143,154,169],"measured":[127,144],"13.1":[129],"GB/s":[130,136,147],"read":[132],"operation":[133],"12.1":[135],"write":[138],"operation.":[139],"FPGA-to-memory":[141],"64.5":[146],"in":[148],"total.":[149],"An":[150],"AES":[152],"kernel":[153],"selected":[155],"test":[157,163],"multi-FPGA":[160],"architecture.":[161],"throughput":[168,177],"achiveded":[170],"when":[171],"FPGAs":[173],"used.":[175],"per":[178],"watt":[179],"shows":[180],"5\u00d7":[181],"improvement":[182],"four":[184],"over":[186],"general-purpose":[188],"processor.":[189]},"counts_by_year":[{"year":2021,"cited_by_count":4},{"year":2018,"cited_by_count":9},{"year":2017,"cited_by_count":4},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":3}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
