{"id":"https://openalex.org/W2090236435","doi":"https://doi.org/10.1109/reconfig.2014.7032497","title":"An a-FPGA architecture for relative timing based asynchronous designs","display_name":"An a-FPGA architecture for relative timing based asynchronous designs","publication_year":2014,"publication_date":"2014-12-01","ids":{"openalex":"https://openalex.org/W2090236435","doi":"https://doi.org/10.1109/reconfig.2014.7032497","mag":"2090236435"},"language":"en","primary_location":{"id":"doi:10.1109/reconfig.2014.7032497","is_oa":false,"landing_page_url":"https://doi.org/10.1109/reconfig.2014.7032497","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5079660330","display_name":"Jotham Vaddaboina Manoranjan","orcid":null},"institutions":[{"id":"https://openalex.org/I223532165","display_name":"University of Utah","ror":"https://ror.org/03r0ha626","country_code":"US","type":"education","lineage":["https://openalex.org/I223532165"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jotham Vaddaboina Manoranjan","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Utah"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Utah","institution_ids":["https://openalex.org/I223532165"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5113695022","display_name":"Kenneth S. Stevens","orcid":null},"institutions":[{"id":"https://openalex.org/I223532165","display_name":"University of Utah","ror":"https://ror.org/03r0ha626","country_code":"US","type":"education","lineage":["https://openalex.org/I223532165"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kenneth S. Stevens","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Utah"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Utah","institution_ids":["https://openalex.org/I223532165"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I223532165"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.18173497,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.8735887408256531},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7533931136131287},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7113896012306213},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.6813100576400757},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5600165128707886},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.4660806357860565},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.43630725145339966},{"id":"https://openalex.org/keywords/asynchronous-system","display_name":"Asynchronous system","score":0.43060770630836487},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.14952382445335388},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.057642221450805664}],"concepts":[{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.8735887408256531},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7533931136131287},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7113896012306213},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.6813100576400757},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5600165128707886},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.4660806357860565},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.43630725145339966},{"id":"https://openalex.org/C7923308","wikidata":"https://www.wikidata.org/wiki/Q4812211","display_name":"Asynchronous system","level":5,"score":0.43060770630836487},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.14952382445335388},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.057642221450805664},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.0},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/reconfig.2014.7032497","is_oa":false,"landing_page_url":"https://doi.org/10.1109/reconfig.2014.7032497","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Sustainable cities and communities","id":"https://metadata.un.org/sdg/11","score":0.4399999976158142}],"awards":[],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":30,"referenced_works":["https://openalex.org/W1527137186","https://openalex.org/W1577323490","https://openalex.org/W1593566378","https://openalex.org/W1657311214","https://openalex.org/W1726603752","https://openalex.org/W1747959818","https://openalex.org/W1975165972","https://openalex.org/W1982876335","https://openalex.org/W1986785033","https://openalex.org/W2013954191","https://openalex.org/W2018257140","https://openalex.org/W2107135459","https://openalex.org/W2125198382","https://openalex.org/W2126172352","https://openalex.org/W2128189348","https://openalex.org/W2130552249","https://openalex.org/W2137541450","https://openalex.org/W2146127897","https://openalex.org/W2146778320","https://openalex.org/W2164162813","https://openalex.org/W2164337590","https://openalex.org/W2167251228","https://openalex.org/W2167775755","https://openalex.org/W4236249998","https://openalex.org/W4245439186","https://openalex.org/W4298011152","https://openalex.org/W4298857929","https://openalex.org/W6635545966","https://openalex.org/W6684175243","https://openalex.org/W6684191323"],"related_works":["https://openalex.org/W3146360095","https://openalex.org/W4312516786","https://openalex.org/W2129978639","https://openalex.org/W2362759320","https://openalex.org/W2279224052","https://openalex.org/W2545105736","https://openalex.org/W304800142","https://openalex.org/W2770353918","https://openalex.org/W2388325543","https://openalex.org/W137380470"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"an":[3],"asynchronous":[4,15,35],"FPGA":[5],"architecture":[6,18,23,49,73],"that":[7,31],"is":[8,54],"capable":[9,37],"of":[10,64,85],"implementing":[11],"relative":[12],"timing":[13],"based":[14],"designs.":[16,45],"The":[17,72],"uses":[19],"the":[20,48,59,62,65,86],"Xilinx":[21],"7-Series":[22],"as":[24],"a":[25],"starting":[26],"point":[27],"and":[28,79],"proposes":[29],"modifications":[30],"would":[32],"make":[33],"it":[34,40,53],"design":[36],"while":[38],"keeping":[39],"fully":[41],"functional":[42],"for":[43],"synchronous":[44,87],"Even":[46],"though":[47],"requires":[50],"additional":[51],"components,":[52],"observed":[55],"when":[56],"implemented":[57],"on":[58,83],"64-nm":[60],"node,":[61],"area":[63],"slice":[66],"was":[67],"increases":[68],"marginally":[69],"by":[70],"7%.":[71],"leaves":[74],"configurable":[75],"routing":[76],"structures":[77],"untouched":[78],"does":[80],"not":[81],"compromise":[82],"performance":[84],"architecture.":[88]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2021,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}