{"id":"https://openalex.org/W2028848594","doi":"https://doi.org/10.1109/reconfig.2013.6732320","title":"PolyNOC — A polymorphic thread simulator for NoC communication based embedded systems","display_name":"PolyNOC — A polymorphic thread simulator for NoC communication based embedded systems","publication_year":2013,"publication_date":"2013-12-01","ids":{"openalex":"https://openalex.org/W2028848594","doi":"https://doi.org/10.1109/reconfig.2013.6732320","mag":"2028848594"},"language":"en","primary_location":{"id":"doi:10.1109/reconfig.2013.6732320","is_oa":false,"landing_page_url":"https://doi.org/10.1109/reconfig.2013.6732320","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 International Conference on Reconfigurable Computing and FPGAs (ReConFig)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5066897414","display_name":"Swamy D. Ponpandi","orcid":null},"institutions":[{"id":"https://openalex.org/I173911158","display_name":"Iowa State University","ror":"https://ror.org/04rswrd78","country_code":"US","type":"education","lineage":["https://openalex.org/I173911158"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Swamy D. Ponpandi","raw_affiliation_strings":["Dept. of Electrical and Computer Engineering, Iowa State University, Ames, Iowa, USA","Dept. of Electr. & Comput. Eng., Iowa State Univ., Ames, IA, USA#TAB#"],"affiliations":[{"raw_affiliation_string":"Dept. of Electrical and Computer Engineering, Iowa State University, Ames, Iowa, USA","institution_ids":["https://openalex.org/I173911158"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Iowa State Univ., Ames, IA, USA#TAB#","institution_ids":["https://openalex.org/I173911158"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100599312","display_name":"Zhang Zhang","orcid":"https://orcid.org/0000-0002-3510-4585"},"institutions":[{"id":"https://openalex.org/I173911158","display_name":"Iowa State University","ror":"https://ror.org/04rswrd78","country_code":"US","type":"education","lineage":["https://openalex.org/I173911158"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Zhang Zhang","raw_affiliation_strings":["Dept. of Electrical and Computer Engineering, Iowa State University, Ames, Iowa, USA","Dept. of Electr. & Comput. Eng., Iowa State Univ., Ames, IA, USA#TAB#"],"affiliations":[{"raw_affiliation_string":"Dept. of Electrical and Computer Engineering, Iowa State University, Ames, Iowa, USA","institution_ids":["https://openalex.org/I173911158"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Iowa State Univ., Ames, IA, USA#TAB#","institution_ids":["https://openalex.org/I173911158"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5102977539","display_name":"Akhilesh Tyagi","orcid":"https://orcid.org/0000-0002-2101-3594"},"institutions":[{"id":"https://openalex.org/I173911158","display_name":"Iowa State University","ror":"https://ror.org/04rswrd78","country_code":"US","type":"education","lineage":["https://openalex.org/I173911158"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Akhilesh Tyagi","raw_affiliation_strings":["Dept. of Electrical and Computer Engineering, Iowa State University, Ames, Iowa, USA","Dept. of Electr. & Comput. Eng., Iowa State Univ., Ames, IA, USA#TAB#"],"affiliations":[{"raw_affiliation_string":"Dept. of Electrical and Computer Engineering, Iowa State University, Ames, Iowa, USA","institution_ids":["https://openalex.org/I173911158"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Iowa State Univ., Ames, IA, USA#TAB#","institution_ids":["https://openalex.org/I173911158"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5066897414"],"corresponding_institution_ids":["https://openalex.org/I173911158"],"apc_list":null,"apc_paid":null,"fwci":0.36207187,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.6606017,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"1","issue":null,"first_page":"1","last_page":"8"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7783511877059937},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.6087178587913513},{"id":"https://openalex.org/keywords/thread","display_name":"Thread (computing)","score":0.5954863429069519},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5824726819992065},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5445984601974487},{"id":"https://openalex.org/keywords/user-satisfaction","display_name":"User satisfaction","score":0.5404651165008545},{"id":"https://openalex.org/keywords/network-on-a-chip","display_name":"Network on a chip","score":0.5357818603515625},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.46963831782341003},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.4440914988517761},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.32516470551490784},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.24809560179710388},{"id":"https://openalex.org/keywords/human\u2013computer-interaction","display_name":"Human\u2013computer interaction","score":0.1369630992412567},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.10309883952140808}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7783511877059937},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.6087178587913513},{"id":"https://openalex.org/C138101251","wikidata":"https://www.wikidata.org/wiki/Q213092","display_name":"Thread (computing)","level":2,"score":0.5954863429069519},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5824726819992065},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5445984601974487},{"id":"https://openalex.org/C3017893058","wikidata":"https://www.wikidata.org/wiki/Q999278","display_name":"User satisfaction","level":2,"score":0.5404651165008545},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.5357818603515625},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.46963831782341003},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.4440914988517761},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.32516470551490784},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.24809560179710388},{"id":"https://openalex.org/C107457646","wikidata":"https://www.wikidata.org/wiki/Q207434","display_name":"Human\u2013computer interaction","level":1,"score":0.1369630992412567},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.10309883952140808},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/reconfig.2013.6732320","is_oa":false,"landing_page_url":"https://doi.org/10.1109/reconfig.2013.6732320","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 International Conference on Reconfigurable Computing and FPGAs (ReConFig)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.44999998807907104,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W2001304594","https://openalex.org/W2079942837","https://openalex.org/W2098457084","https://openalex.org/W2098572701","https://openalex.org/W2099714261","https://openalex.org/W2105853930","https://openalex.org/W2116007187","https://openalex.org/W2118052934","https://openalex.org/W2129442721","https://openalex.org/W2144357574","https://openalex.org/W2153331583","https://openalex.org/W2160955218","https://openalex.org/W2172272388","https://openalex.org/W3151080728","https://openalex.org/W4236433846","https://openalex.org/W6678774128"],"related_works":["https://openalex.org/W4863605","https://openalex.org/W4285287318","https://openalex.org/W2388672758","https://openalex.org/W2502691491","https://openalex.org/W2135981148","https://openalex.org/W2754086592","https://openalex.org/W2144357574","https://openalex.org/W2784141701","https://openalex.org/W3142211975","https://openalex.org/W1978899622"],"abstract_inverted_index":{"Integration":[0],"of":[1,24,44,48,60,93,117],"multiple":[2],"processing":[3],"cores":[4],"and":[5,95,102],"variegated":[6],"custom":[7],"hardware":[8],"functional":[9],"units":[10],"in":[11,78,122],"recent":[12],"embedded":[13,34,82],"system":[14,46,83],"chips":[15],"favor":[16],"network-on-chip":[17],"(NOC)":[18],"communication":[19],"architecture":[20],"for":[21,32,75,90,114],"optimal":[22,115],"utilization":[23,116],"these":[25],"components":[26],"by":[27],"applications.":[28],"Application":[29],"design":[30,51],"paradigms":[31],"such":[33,53],"systems":[35],"should":[36],"aim":[37],"to":[38,71],"improve":[39],"the":[40,45],"overall":[41],"user":[42,66,73,124],"experience":[43,74],"instead":[47],"optimizing":[49],"traditional":[50],"parameters":[52],"as":[54],"power,":[55],"speed":[56],"or":[57],"some":[58],"combination":[59],"these.":[61],"In":[62],"this":[63],"paper,":[64],"a":[65],"satisfaction":[67,87],"model":[68],"is":[69,98,110],"used":[70],"capture":[72],"multimedia":[76],"applications":[77],"an":[79,111],"NOC":[80,118],"based":[81,88],"simulation":[84],"tool.":[85],"User":[86],"scheduling":[89,104],"polymorphic":[91],"implementation":[92],"video":[94],"audio":[96],"application":[97],"compared":[99],"against":[100],"FCFS":[101],"EDF":[103],"policies.":[105],"Experiments":[106],"demonstrate":[107],"that":[108,120],"polymorphism":[109],"effective":[112],"technique":[113],"resources":[119],"results":[121],"improved":[123],"satisfaction.":[125]},"counts_by_year":[{"year":2015,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}