{"id":"https://openalex.org/W2032253216","doi":"https://doi.org/10.1109/reconfig.2013.6732302","title":"Improving FPGA placement with a self-organizing map","display_name":"Improving FPGA placement with a self-organizing map","publication_year":2013,"publication_date":"2013-12-01","ids":{"openalex":"https://openalex.org/W2032253216","doi":"https://doi.org/10.1109/reconfig.2013.6732302","mag":"2032253216"},"language":"en","primary_location":{"id":"doi:10.1109/reconfig.2013.6732302","is_oa":false,"landing_page_url":"https://doi.org/10.1109/reconfig.2013.6732302","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 International Conference on Reconfigurable Computing and FPGAs (ReConFig)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5006335623","display_name":"Timm Bostelmann","orcid":null},"institutions":[{"id":"https://openalex.org/I113463164","display_name":"University of Applied Sciences Wedel","ror":"https://ror.org/00bwfj843","country_code":"DE","type":"education","lineage":["https://openalex.org/I113463164"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Timm Bostelmann","raw_affiliation_strings":["FH Wedel (University of Applied Sciences), Wedel","FH Wedel (Univ. of Appl. Sci.), Wedel, Germany"],"affiliations":[{"raw_affiliation_string":"FH Wedel (University of Applied Sciences), Wedel","institution_ids":["https://openalex.org/I113463164"]},{"raw_affiliation_string":"FH Wedel (Univ. of Appl. Sci.), Wedel, Germany","institution_ids":["https://openalex.org/I113463164"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5110272995","display_name":"Sergei Sawitzki","orcid":null},"institutions":[{"id":"https://openalex.org/I113463164","display_name":"University of Applied Sciences Wedel","ror":"https://ror.org/00bwfj843","country_code":"DE","type":"education","lineage":["https://openalex.org/I113463164"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Sergei Sawitzki","raw_affiliation_strings":["FH Wedel (University of Applied Sciences), Wedel","FH Wedel (Univ. of Appl. Sci.), Wedel, Germany"],"affiliations":[{"raw_affiliation_string":"FH Wedel (University of Applied Sciences), Wedel","institution_ids":["https://openalex.org/I113463164"]},{"raw_affiliation_string":"FH Wedel (Univ. of Appl. Sci.), Wedel, Germany","institution_ids":["https://openalex.org/I113463164"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5006335623"],"corresponding_institution_ids":["https://openalex.org/I113463164"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.09436998,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"179","issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9959999918937683,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/netlist","display_name":"Netlist","score":0.946877658367157},{"id":"https://openalex.org/keywords/initialization","display_name":"Initialization","score":0.8046469688415527},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7474174499511719},{"id":"https://openalex.org/keywords/simulated-annealing","display_name":"Simulated annealing","score":0.7141659259796143},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.632712185382843},{"id":"https://openalex.org/keywords/placement","display_name":"Placement","score":0.622388482093811},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.5697093605995178},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.4492191970348358},{"id":"https://openalex.org/keywords/iterative-method","display_name":"Iterative method","score":0.41303732991218567},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.39036011695861816},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3509686589241028},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3317687511444092},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.28823673725128174},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.16129931807518005},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.08794617652893066}],"concepts":[{"id":"https://openalex.org/C177650935","wikidata":"https://www.wikidata.org/wiki/Q1760303","display_name":"Netlist","level":2,"score":0.946877658367157},{"id":"https://openalex.org/C114466953","wikidata":"https://www.wikidata.org/wiki/Q6034165","display_name":"Initialization","level":2,"score":0.8046469688415527},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7474174499511719},{"id":"https://openalex.org/C126980161","wikidata":"https://www.wikidata.org/wiki/Q863783","display_name":"Simulated annealing","level":2,"score":0.7141659259796143},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.632712185382843},{"id":"https://openalex.org/C117690923","wikidata":"https://www.wikidata.org/wiki/Q1484784","display_name":"Placement","level":4,"score":0.622388482093811},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.5697093605995178},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.4492191970348358},{"id":"https://openalex.org/C159694833","wikidata":"https://www.wikidata.org/wiki/Q2321565","display_name":"Iterative method","level":2,"score":0.41303732991218567},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.39036011695861816},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3509686589241028},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3317687511444092},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.28823673725128174},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.16129931807518005},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.08794617652893066},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/reconfig.2013.6732302","is_oa":false,"landing_page_url":"https://doi.org/10.1109/reconfig.2013.6732302","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 International Conference on Reconfigurable Computing and FPGAs (ReConFig)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/15","display_name":"Life in Land","score":0.5400000214576721}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W50122904","https://openalex.org/W115204829","https://openalex.org/W1538471030","https://openalex.org/W2011039300","https://openalex.org/W2024060531","https://openalex.org/W2024338444","https://openalex.org/W2025516544","https://openalex.org/W2067387861","https://openalex.org/W2085374061","https://openalex.org/W2114257558","https://openalex.org/W2117082818","https://openalex.org/W2139637699","https://openalex.org/W2164132095","https://openalex.org/W2953167458","https://openalex.org/W3123791793","https://openalex.org/W3148293037","https://openalex.org/W3203992401","https://openalex.org/W4213332169","https://openalex.org/W6632236923","https://openalex.org/W6637174430","https://openalex.org/W6667225350"],"related_works":["https://openalex.org/W2385394209","https://openalex.org/W1987487129","https://openalex.org/W2164654367","https://openalex.org/W2169510384","https://openalex.org/W1968897524","https://openalex.org/W2086835975","https://openalex.org/W1483430493","https://openalex.org/W2032253216","https://openalex.org/W2121263056","https://openalex.org/W1557016741"],"abstract_inverted_index":{"This":[0,42],"work":[1],"shows":[2],"how":[3],"the":[4,17,52,63,66,70,79],"results":[5],"of":[6,19,26,65],"netlist":[7,28],"placement":[8,50],"for":[9,51],"island":[10],"style":[11],"FPGAs":[12],"can":[13],"be":[14],"improved":[15],"by":[16,38],"use":[18],"a":[20,27,39],"self-organizing":[21,40],"map.":[22,41],"The":[23],"structural":[24],"information":[25],"is":[29,44],"used":[30,45],"to":[31,46,78],"generate":[32,47],"training":[33],"vectors,":[34],"which":[35],"are":[36,74],"classified":[37],"classification":[43],"an":[48],"initial":[49],"renown":[53],"iterative":[54],"simulated":[55],"annealing":[56],"algorithm.":[57],"By":[58],"applying":[59],"this":[60],"procedure":[61],"both":[62],"length":[64],"critical":[67],"path":[68],"and":[69],"needed":[71],"routing":[72],"resources":[73],"reduced":[75],"in":[76],"comparison":[77],"classical":[80],"random":[81],"initialization.":[82]},"counts_by_year":[{"year":2017,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}