{"id":"https://openalex.org/W2030402530","doi":"https://doi.org/10.1109/reconfig.2013.6732288","title":"Exploration environment for 3D heterogeneous tree-based FPGA architectures (3D HT-FPGA)","display_name":"Exploration environment for 3D heterogeneous tree-based FPGA architectures (3D HT-FPGA)","publication_year":2013,"publication_date":"2013-12-01","ids":{"openalex":"https://openalex.org/W2030402530","doi":"https://doi.org/10.1109/reconfig.2013.6732288","mag":"2030402530"},"language":"en","primary_location":{"id":"doi:10.1109/reconfig.2013.6732288","is_oa":false,"landing_page_url":"https://doi.org/10.1109/reconfig.2013.6732288","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 International Conference on Reconfigurable Computing and FPGAs (ReConFig)","raw_type":"proceedings-article"},"type":"preprint","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5044271464","display_name":"Vinod Pangracious","orcid":"https://orcid.org/0000-0002-4240-6610"},"institutions":[{"id":"https://openalex.org/I117023288","display_name":"Analog Devices (United States)","ror":"https://ror.org/01545pm61","country_code":"US","type":"company","lineage":["https://openalex.org/I117023288"]},{"id":"https://openalex.org/I39804081","display_name":"Sorbonne Universit\u00e9","ror":"https://ror.org/02en5vm52","country_code":"FR","type":"education","lineage":["https://openalex.org/I39804081"]}],"countries":["FR","US"],"is_corresponding":false,"raw_author_name":"Vinod Pangracious","raw_affiliation_strings":["LIP6/University Pierre and Marie Curie, Paris VI","Circuits Int\u00e9gr\u00e9s Num\u00e9riques et Analogiques"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"LIP6/University Pierre and Marie Curie, Paris VI","institution_ids":["https://openalex.org/I39804081"]},{"raw_affiliation_string":"Circuits Int\u00e9gr\u00e9s Num\u00e9riques et Analogiques","institution_ids":["https://openalex.org/I117023288"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5108405631","display_name":"Habib Mehrez","orcid":null},"institutions":[{"id":"https://openalex.org/I117023288","display_name":"Analog Devices (United States)","ror":"https://ror.org/01545pm61","country_code":"US","type":"company","lineage":["https://openalex.org/I117023288"]},{"id":"https://openalex.org/I39804081","display_name":"Sorbonne Universit\u00e9","ror":"https://ror.org/02en5vm52","country_code":"FR","type":"education","lineage":["https://openalex.org/I39804081"]}],"countries":["FR","US"],"is_corresponding":false,"raw_author_name":"Habib Mehrez","raw_affiliation_strings":["LIP6/University Pierre and Marie Curie, Paris VI","Circuits Int\u00e9gr\u00e9s Num\u00e9riques et Analogiques"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"LIP6/University Pierre and Marie Curie, Paris VI","institution_ids":["https://openalex.org/I39804081"]},{"raw_affiliation_string":"Circuits Int\u00e9gr\u00e9s Num\u00e9riques et Analogiques","institution_ids":["https://openalex.org/I117023288"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5048255496","display_name":"Nizar Beltaief","orcid":null},"institutions":[{"id":"https://openalex.org/I117023288","display_name":"Analog Devices (United States)","ror":"https://ror.org/01545pm61","country_code":"US","type":"company","lineage":["https://openalex.org/I117023288"]},{"id":"https://openalex.org/I39804081","display_name":"Sorbonne Universit\u00e9","ror":"https://ror.org/02en5vm52","country_code":"FR","type":"education","lineage":["https://openalex.org/I39804081"]}],"countries":["FR","US"],"is_corresponding":false,"raw_author_name":"Nizar Beltaief","raw_affiliation_strings":["LIP6/University Pierre and Marie Curie, Paris VI","Circuits Int\u00e9gr\u00e9s Num\u00e9riques et Analogiques"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"LIP6/University Pierre and Marie Curie, Paris VI","institution_ids":["https://openalex.org/I39804081"]},{"raw_affiliation_string":"Circuits Int\u00e9gr\u00e9s Num\u00e9riques et Analogiques","institution_ids":["https://openalex.org/I117023288"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111822030","display_name":"Zied Marrakchi","orcid":null},"institutions":[{"id":"https://openalex.org/I117023288","display_name":"Analog Devices (United States)","ror":"https://ror.org/01545pm61","country_code":"US","type":"company","lineage":["https://openalex.org/I117023288"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Zied Marrakchi","raw_affiliation_strings":["FLEXRAS Technologies","Circuits Int\u00e9gr\u00e9s Num\u00e9riques et Analogiques","Flexras Technologies"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"FLEXRAS Technologies","institution_ids":[]},{"raw_affiliation_string":"Circuits Int\u00e9gr\u00e9s Num\u00e9riques et Analogiques","institution_ids":["https://openalex.org/I117023288"]},{"raw_affiliation_string":"Flexras Technologies","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5088890905","display_name":"Umer Farooq","orcid":"https://orcid.org/0000-0002-5220-4908"},"institutions":[{"id":"https://openalex.org/I16076960","display_name":"COMSATS University Islamabad","ror":"https://ror.org/00nqqvk19","country_code":"PK","type":"education","lineage":["https://openalex.org/I16076960"]}],"countries":["PK"],"is_corresponding":false,"raw_author_name":"Umer Farooq","raw_affiliation_strings":["COMSATS IIT, Pakistan","COMSATS IIT Pakistan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"COMSATS IIT, Pakistan","institution_ids":["https://openalex.org/I16076960"]},{"raw_affiliation_string":"COMSATS IIT Pakistan","institution_ids":["https://openalex.org/I16076960"]}]}],"institutions":[],"countries_distinct_count":3,"institutions_distinct_count":5,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.12795938,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"7806","issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9972000122070312,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8317339420318604},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7523156404495239},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.6402102112770081},{"id":"https://openalex.org/keywords/tree","display_name":"Tree (set theory)","score":0.5917944312095642},{"id":"https://openalex.org/keywords/tree-network","display_name":"Tree network","score":0.5405979752540588},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.49312230944633484},{"id":"https://openalex.org/keywords/footprint","display_name":"Footprint","score":0.4646325409412384},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4271673262119293},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.14553099870681763},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.1430167257785797},{"id":"https://openalex.org/keywords/time-complexity","display_name":"Time complexity","score":0.12351274490356445}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8317339420318604},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7523156404495239},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.6402102112770081},{"id":"https://openalex.org/C113174947","wikidata":"https://www.wikidata.org/wiki/Q2859736","display_name":"Tree (set theory)","level":2,"score":0.5917944312095642},{"id":"https://openalex.org/C2781010653","wikidata":"https://www.wikidata.org/wiki/Q12056602","display_name":"Tree network","level":3,"score":0.5405979752540588},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.49312230944633484},{"id":"https://openalex.org/C132943942","wikidata":"https://www.wikidata.org/wiki/Q2562511","display_name":"Footprint","level":2,"score":0.4646325409412384},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4271673262119293},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.14553099870681763},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.1430167257785797},{"id":"https://openalex.org/C311688","wikidata":"https://www.wikidata.org/wiki/Q2393193","display_name":"Time complexity","level":2,"score":0.12351274490356445},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/reconfig.2013.6732288","is_oa":false,"landing_page_url":"https://doi.org/10.1109/reconfig.2013.6732288","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 International Conference on Reconfigurable Computing and FPGAs (ReConFig)","raw_type":"proceedings-article"},{"id":"pmh:oai:HAL:hal-01372829v1","is_oa":false,"landing_page_url":"https://hal.science/hal-01372829","pdf_url":null,"source":{"id":"https://openalex.org/S4306402512","display_name":"HAL (Le Centre pour la Communication Scientifique Directe)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1294671590","host_organization_name":"Centre National de la Recherche Scientifique","host_organization_lineage":["https://openalex.org/I1294671590"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"ReConFig 2013 - International Conference on Reconfigurable Computing and FPGAs, Dec 2013, Cancun, Mexico. pp.1--6, ⟨10.1109/ReConFig.2013.6732288⟩","raw_type":"Conference papers"},{"id":"pmh:oai:sure.sunderland.ac.uk:16367","is_oa":false,"landing_page_url":"https://ieeexplore.ieee.org/abstract/document/6732288","pdf_url":null,"source":{"id":"https://openalex.org/S4306402295","display_name":"Sunderland Repository (University of Sunderland)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I5728261","host_organization_name":"University of Sunderland","host_organization_lineage":["https://openalex.org/I5728261"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"PeerReviewed"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8299999833106995}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W68733363","https://openalex.org/W1581887721","https://openalex.org/W2026717319","https://openalex.org/W2047199967","https://openalex.org/W2070608594","https://openalex.org/W2132668926","https://openalex.org/W2152446494","https://openalex.org/W2157890680","https://openalex.org/W2171626895"],"related_works":["https://openalex.org/W2346214237","https://openalex.org/W2074659255","https://openalex.org/W4226003002","https://openalex.org/W2161760510","https://openalex.org/W2157047836","https://openalex.org/W2361857689","https://openalex.org/W2751262944","https://openalex.org/W2259163152","https://openalex.org/W2919537010","https://openalex.org/W4288328148"],"abstract_inverted_index":{"We":[0,100],"describe":[1],"the":[2,28,37,47,70,82,92,96,103,110,115],"physical":[3],"design":[4,54],"and":[5,32,75,106,119,123,133,143,150],"exploration":[6],"methodology":[7],"to":[8,26,39,68,90,157],"optimize":[9,27,91],"3-dimensional":[10],"(3D)":[11],"heterogeneous":[12],"Tree-based":[13],"FPGA":[14],"(HT-FPGA)":[15],"by":[16,131,139,154],"introducing":[17],"a":[18,21,41,57],"break-point":[19,61,83],"at":[20],"particular":[22],"tree":[23,50,65,87,98],"level":[24],"interconnect":[25,93],"speed,":[29],"power":[30,107,151],"consumption":[31,108,152],"area.":[33],"The":[34,60],"ability":[35],"of":[36,46,62,72,84,95,109],"flow":[38,118],"decide":[40],"horizontal":[42,147],"or":[43],"vertical":[44,122,142],"partitioning":[45,148],"multilevel":[48],"programmable":[49,97],"network":[51],"based":[52],"on":[53],"specifications":[55],"is":[56,66,88],"defining":[58],"feature.":[59],"vertically":[63],"partitioned":[64,86,125],"designed":[67,89],"balance":[69],"placement":[71],"logic":[73],"blocks":[74,77],"switch":[76],"into":[78],"multiple":[79],"tiers":[80],"while":[81],"horizontally":[85,124],"delay":[94],"network.":[99],"finally":[101],"evaluate":[102],"performance,":[104],"area":[105],"proposed":[111],"3D":[112,126],"HT-FPGA":[113,128],"using":[114],"newly":[116],"developed":[117],"show":[120],"that":[121],"stacked":[127],"improves":[129],"speed":[130],"16%":[132],"55%":[134],"respectively.":[135],"Silicon":[136],"footprint":[137],"reduced":[138,153],"50%":[140],"for":[141,146],"46":[144],"%":[145],"method":[149],"35%":[155],"compared":[156],"2D":[158],"counterpart.":[159]},"counts_by_year":[{"year":2018,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}