{"id":"https://openalex.org/W2048887547","doi":"https://doi.org/10.1109/reconfig.2013.6732287","title":"Exploiting architecture description language for diverse IP synthesis in heterogeneous MPSoC","display_name":"Exploiting architecture description language for diverse IP synthesis in heterogeneous MPSoC","publication_year":2013,"publication_date":"2013-12-01","ids":{"openalex":"https://openalex.org/W2048887547","doi":"https://doi.org/10.1109/reconfig.2013.6732287","mag":"2048887547"},"language":"en","primary_location":{"id":"doi:10.1109/reconfig.2013.6732287","is_oa":false,"landing_page_url":"https://doi.org/10.1109/reconfig.2013.6732287","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 International Conference on Reconfigurable Computing and FPGAs (ReConFig)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5003213489","display_name":"Zolt\u00e1n Endre R\u00e1kossy","orcid":null},"institutions":[{"id":"https://openalex.org/I887968799","display_name":"RWTH Aachen University","ror":"https://ror.org/04xfq0f34","country_code":"DE","type":"education","lineage":["https://openalex.org/I887968799"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Zoltan Endre Rakossy","raw_affiliation_strings":["Institute for Communication Technologies and Embedded Systems (ICE), RWTH University, Aachen, Germany","Inst. for Commun. Technol. & Embedded Syst. (ICE), RWTH Aachen Univ., Aachen, Germany"],"affiliations":[{"raw_affiliation_string":"Institute for Communication Technologies and Embedded Systems (ICE), RWTH University, Aachen, Germany","institution_ids":["https://openalex.org/I887968799"]},{"raw_affiliation_string":"Inst. for Commun. Technol. & Embedded Syst. (ICE), RWTH Aachen Univ., Aachen, Germany","institution_ids":["https://openalex.org/I887968799"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5001816933","display_name":"Axel Acosta Aponte","orcid":null},"institutions":[{"id":"https://openalex.org/I887968799","display_name":"RWTH Aachen University","ror":"https://ror.org/04xfq0f34","country_code":"DE","type":"education","lineage":["https://openalex.org/I887968799"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Axel Acosta Aponte","raw_affiliation_strings":["Institute for Communication Technologies and Embedded Systems (ICE), RWTH University, Aachen, Germany","Inst. for Commun. Technol. & Embedded Syst. (ICE), RWTH Aachen Univ., Aachen, Germany"],"affiliations":[{"raw_affiliation_string":"Institute for Communication Technologies and Embedded Systems (ICE), RWTH University, Aachen, Germany","institution_ids":["https://openalex.org/I887968799"]},{"raw_affiliation_string":"Inst. for Commun. Technol. & Embedded Syst. (ICE), RWTH Aachen Univ., Aachen, Germany","institution_ids":["https://openalex.org/I887968799"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5089860351","display_name":"Anupam Chattopadhyay","orcid":"https://orcid.org/0000-0002-8818-6983"},"institutions":[{"id":"https://openalex.org/I887968799","display_name":"RWTH Aachen University","ror":"https://ror.org/04xfq0f34","country_code":"DE","type":"education","lineage":["https://openalex.org/I887968799"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Anupam Chattopadhyay","raw_affiliation_strings":["Institute for Communication Technologies and Embedded Systems (ICE), RWTH University, Aachen, Germany","Inst. for Commun. Technol. & Embedded Syst. (ICE), RWTH Aachen Univ., Aachen, Germany"],"affiliations":[{"raw_affiliation_string":"Institute for Communication Technologies and Embedded Systems (ICE), RWTH University, Aachen, Germany","institution_ids":["https://openalex.org/I887968799"]},{"raw_affiliation_string":"Inst. for Commun. Technol. & Embedded Syst. (ICE), RWTH Aachen Univ., Aachen, Germany","institution_ids":["https://openalex.org/I887968799"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5003213489"],"corresponding_institution_ids":["https://openalex.org/I887968799"],"apc_list":null,"apc_paid":null,"fwci":1.8991,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.8585702,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":"17","issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.7768959403038025},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7457332611083984},{"id":"https://openalex.org/keywords/flexibility","display_name":"Flexibility (engineering)","score":0.737463116645813},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.7145589590072632},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.6791300773620605},{"id":"https://openalex.org/keywords/exploit","display_name":"Exploit","score":0.6710445880889893},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.5845199227333069},{"id":"https://openalex.org/keywords/mpsoc","display_name":"MPSoC","score":0.5331854820251465},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.5111268162727356},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4254646599292755},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.34976738691329956},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.32054707407951355}],"concepts":[{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.7768959403038025},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7457332611083984},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.737463116645813},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.7145589590072632},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.6791300773620605},{"id":"https://openalex.org/C165696696","wikidata":"https://www.wikidata.org/wiki/Q11287","display_name":"Exploit","level":2,"score":0.6710445880889893},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.5845199227333069},{"id":"https://openalex.org/C2777187653","wikidata":"https://www.wikidata.org/wiki/Q975106","display_name":"MPSoC","level":3,"score":0.5331854820251465},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.5111268162727356},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4254646599292755},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.34976738691329956},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.32054707407951355},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/reconfig.2013.6732287","is_oa":false,"landing_page_url":"https://doi.org/10.1109/reconfig.2013.6732287","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 International Conference on Reconfigurable Computing and FPGAs (ReConFig)","raw_type":"proceedings-article"},{"id":"pmh:oai:publications.rwth-aachen.de:463917","is_oa":false,"landing_page_url":"https://publications.rwth-aachen.de/record/463917","pdf_url":null,"source":{"id":"https://openalex.org/S4306401362","display_name":"RWTH Publications (RWTH Aachen)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I887968799","host_organization_name":"RWTH Aachen University","host_organization_lineage":["https://openalex.org/I887968799"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"2013 International Conference on Reconfigurable Computing and FPGAs (ReConFig) : Cancun, Mexico, December 9-11, 2013 /  Rene\u0301 Cumplido; Eduardo de la Torre ; Michael J Wirthlin. Instituto Nacional de Astrofi\u0301sica, Optica y Electro\u0301nica (Mexico) ; Universidad Polite\u0301cnica de Madrid<br/>International Conference on ReConFigurable Computing and FPGAs (ReConFig), ReConFig, Cancun, Mexico, 2013-12-09 - 2013-12-11","raw_type":"info:eu-repo/semantics/publishedVersion"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/11","score":0.5400000214576721,"display_name":"Sustainable cities and communities"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W37085840","https://openalex.org/W83586921","https://openalex.org/W1860992226","https://openalex.org/W1966826470","https://openalex.org/W1997480156","https://openalex.org/W2010074783","https://openalex.org/W2017633437","https://openalex.org/W2039981468","https://openalex.org/W2053238222","https://openalex.org/W2100550266","https://openalex.org/W2112537029","https://openalex.org/W2118229154","https://openalex.org/W2123565700","https://openalex.org/W2127882392","https://openalex.org/W2153883804","https://openalex.org/W2156731210","https://openalex.org/W2159184138","https://openalex.org/W4232714327","https://openalex.org/W4234669735","https://openalex.org/W4246254772","https://openalex.org/W6654848027"],"related_works":["https://openalex.org/W2092181573","https://openalex.org/W2576551918","https://openalex.org/W2056447856","https://openalex.org/W2998838928","https://openalex.org/W2783693002","https://openalex.org/W4281926497","https://openalex.org/W3043614744","https://openalex.org/W2105957719","https://openalex.org/W1973069902","https://openalex.org/W2124403023"],"abstract_inverted_index":{"High":[0],"Level":[1],"Synthesis":[2],"(HLS)":[3],"and":[4,11,21,36,42,57,67,90],"design":[5,19,52,92],"is":[6],"gaining":[7],"traction":[8],"in":[9],"commercial":[10],"academic":[12],"circles,":[13],"as":[14],"an":[15],"answer":[16],"to":[17,40,54,86],"increasing":[18],"complexity":[20],"short":[22,30],"time-to-market.":[23],"In":[24],"this":[25],"paper,":[26],"we":[27],"present":[28],"a":[29,48,83,88],"survey":[31],"on":[32],"the":[33,44,76,79],"HLS":[34],"landscape":[35],"propose":[37],"modeling":[38],"concepts":[39],"extract":[41],"exploit":[43],"inherent":[45],"flexibility":[46,66],"for":[47],"commercially":[49],"available":[50],"high-level":[51],"tool,":[53],"explore":[55],"ASIC":[56],"CGRA":[58],"besides":[59],"native":[60],"ASIP":[61],"support.":[62],"Structural":[63],"descriptions,":[64],"representation,":[65],"limitations":[68],"are":[69],"discussed.":[70],"Several":[71],"case":[72],"studies":[73],"help":[74],"highlight":[75],"advantages":[77],"of":[78],"proposed":[80],"methods,":[81],"providing":[82],"solid":[84],"framework":[85],"aid":[87],"broader":[89],"faster":[91],"space":[93],"exploration.":[94]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2015,"cited_by_count":3},{"year":2014,"cited_by_count":3}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}