{"id":"https://openalex.org/W2093992207","doi":"https://doi.org/10.1109/reconfig.2013.6732276","title":"Design of asynchronous systems on FPGA using direct mapping and synchronous specification","display_name":"Design of asynchronous systems on FPGA using direct mapping and synchronous specification","publication_year":2013,"publication_date":"2013-12-01","ids":{"openalex":"https://openalex.org/W2093992207","doi":"https://doi.org/10.1109/reconfig.2013.6732276","mag":"2093992207"},"language":"en","primary_location":{"id":"doi:10.1109/reconfig.2013.6732276","is_oa":false,"landing_page_url":"https://doi.org/10.1109/reconfig.2013.6732276","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 International Conference on Reconfigurable Computing and FPGAs (ReConFig)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5009078527","display_name":"Duarte L. Oliveira","orcid":null},"institutions":[{"id":"https://openalex.org/I107428990","display_name":"Instituto Tecnol\u00f3gico de Aeron\u00e1utica","ror":"https://ror.org/05vh67662","country_code":"BR","type":"education","lineage":["https://openalex.org/I107428990"]}],"countries":["BR"],"is_corresponding":true,"raw_author_name":"Duarte L. Oliveira","raw_affiliation_strings":["Divis\u00e3o de Engenharia Eletr\u00f4nica, Instituto Tecnol\u00f3gico de Aeron\u00e1utica (ITA), S\u00e3o Paulo, Brazil","Div. de Eng. Eletron., Inst. Tecnol. de Aeronaut. (ITA) SJC, Sao Paulo, Brazil"],"affiliations":[{"raw_affiliation_string":"Divis\u00e3o de Engenharia Eletr\u00f4nica, Instituto Tecnol\u00f3gico de Aeron\u00e1utica (ITA), S\u00e3o Paulo, Brazil","institution_ids":["https://openalex.org/I107428990"]},{"raw_affiliation_string":"Div. de Eng. Eletron., Inst. Tecnol. de Aeronaut. (ITA) SJC, Sao Paulo, Brazil","institution_ids":["https://openalex.org/I107428990"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5054970294","display_name":"Diego Bompean","orcid":null},"institutions":[{"id":"https://openalex.org/I107428990","display_name":"Instituto Tecnol\u00f3gico de Aeron\u00e1utica","ror":"https://ror.org/05vh67662","country_code":"BR","type":"education","lineage":["https://openalex.org/I107428990"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Diego Bompean","raw_affiliation_strings":["Divis\u00e3o de Engenharia Eletr\u00f4nica, Instituto Tecnol\u00f3gico de Aeron\u00e1utica (ITA), S\u00e3o Paulo, Brazil","Div. de Eng. Eletron., Inst. Tecnol. de Aeronaut. (ITA) SJC, Sao Paulo, Brazil"],"affiliations":[{"raw_affiliation_string":"Divis\u00e3o de Engenharia Eletr\u00f4nica, Instituto Tecnol\u00f3gico de Aeron\u00e1utica (ITA), S\u00e3o Paulo, Brazil","institution_ids":["https://openalex.org/I107428990"]},{"raw_affiliation_string":"Div. de Eng. Eletron., Inst. Tecnol. de Aeronaut. (ITA) SJC, Sao Paulo, Brazil","institution_ids":["https://openalex.org/I107428990"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5112249506","display_name":"Lester A. Faria","orcid":null},"institutions":[{"id":"https://openalex.org/I107428990","display_name":"Instituto Tecnol\u00f3gico de Aeron\u00e1utica","ror":"https://ror.org/05vh67662","country_code":"BR","type":"education","lineage":["https://openalex.org/I107428990"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Lester A. Faria","raw_affiliation_strings":["Divis\u00e3o de Engenharia Eletr\u00f4nica, Instituto Tecnol\u00f3gico de Aeron\u00e1utica (ITA), S\u00e3o Paulo, Brazil","Div. de Eng. Eletron., Inst. Tecnol. de Aeronaut. (ITA) SJC, Sao Paulo, Brazil"],"affiliations":[{"raw_affiliation_string":"Divis\u00e3o de Engenharia Eletr\u00f4nica, Instituto Tecnol\u00f3gico de Aeron\u00e1utica (ITA), S\u00e3o Paulo, Brazil","institution_ids":["https://openalex.org/I107428990"]},{"raw_affiliation_string":"Div. de Eng. Eletron., Inst. Tecnol. de Aeronaut. (ITA) SJC, Sao Paulo, Brazil","institution_ids":["https://openalex.org/I107428990"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5008815593","display_name":"Joao Luis V. Oliveira","orcid":null},"institutions":[{"id":"https://openalex.org/I4210119805","display_name":"Instituto de Pesca","ror":"https://ror.org/02gcdp811","country_code":"BR","type":"facility","lineage":["https://openalex.org/I4210119805"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Joao Luis V. Oliveira","raw_affiliation_strings":["Departamento de Desenvolvimento de Software, Instituto de Pesquisas Eldorado, S\u00e3o Paulo, Brazil","Dept. de Desenvolvimento de Software, Inst. de Pesquisas Eldorado, Campinas, Brazil"],"affiliations":[{"raw_affiliation_string":"Departamento de Desenvolvimento de Software, Instituto de Pesquisas Eldorado, S\u00e3o Paulo, Brazil","institution_ids":["https://openalex.org/I4210119805"]},{"raw_affiliation_string":"Dept. de Desenvolvimento de Software, Inst. de Pesquisas Eldorado, Campinas, Brazil","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5009078527"],"corresponding_institution_ids":["https://openalex.org/I107428990"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.14331411,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"e80 d","issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.9085433483123779},{"id":"https://openalex.org/keywords/asynchronous-circuit","display_name":"Asynchronous circuit","score":0.8347792029380798},{"id":"https://openalex.org/keywords/asynchronous-system","display_name":"Asynchronous system","score":0.7991465926170349},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7748270630836487},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.7200400233268738},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6934358477592468},{"id":"https://openalex.org/keywords/synchronizer","display_name":"Synchronizer","score":0.6533571481704712},{"id":"https://openalex.org/keywords/finite-state-machine","display_name":"Finite-state machine","score":0.6452351808547974},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.5482873320579529},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.48175787925720215},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.463644415140152},{"id":"https://openalex.org/keywords/skew","display_name":"Skew","score":0.43855106830596924},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.4209928810596466},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.40300872921943665},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4029313921928406},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.3611565828323364},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.3502310514450073},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.24898508191108704},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.1211775541305542},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.07894298434257507}],"concepts":[{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.9085433483123779},{"id":"https://openalex.org/C87695204","wikidata":"https://www.wikidata.org/wiki/Q629971","display_name":"Asynchronous circuit","level":5,"score":0.8347792029380798},{"id":"https://openalex.org/C7923308","wikidata":"https://www.wikidata.org/wiki/Q4812211","display_name":"Asynchronous system","level":5,"score":0.7991465926170349},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7748270630836487},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.7200400233268738},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6934358477592468},{"id":"https://openalex.org/C66727535","wikidata":"https://www.wikidata.org/wiki/Q7662199","display_name":"Synchronizer","level":2,"score":0.6533571481704712},{"id":"https://openalex.org/C167822520","wikidata":"https://www.wikidata.org/wiki/Q176452","display_name":"Finite-state machine","level":2,"score":0.6452351808547974},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.5482873320579529},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.48175787925720215},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.463644415140152},{"id":"https://openalex.org/C43711488","wikidata":"https://www.wikidata.org/wiki/Q7534783","display_name":"Skew","level":2,"score":0.43855106830596924},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.4209928810596466},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.40300872921943665},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4029313921928406},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3611565828323364},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.3502310514450073},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.24898508191108704},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.1211775541305542},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.07894298434257507},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/reconfig.2013.6732276","is_oa":false,"landing_page_url":"https://doi.org/10.1109/reconfig.2013.6732276","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 International Conference on Reconfigurable Computing and FPGAs (ReConFig)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":34,"referenced_works":["https://openalex.org/W1506034564","https://openalex.org/W1523871158","https://openalex.org/W1554812212","https://openalex.org/W1577323490","https://openalex.org/W1665361481","https://openalex.org/W1726603752","https://openalex.org/W1986303107","https://openalex.org/W1991980662","https://openalex.org/W1999538298","https://openalex.org/W2012845553","https://openalex.org/W2013876999","https://openalex.org/W2014984434","https://openalex.org/W2036605181","https://openalex.org/W2044229916","https://openalex.org/W2049443371","https://openalex.org/W2058948603","https://openalex.org/W2060139911","https://openalex.org/W2085176118","https://openalex.org/W2097085322","https://openalex.org/W2111139814","https://openalex.org/W2111489015","https://openalex.org/W2115894212","https://openalex.org/W2124260068","https://openalex.org/W2135781151","https://openalex.org/W2136138749","https://openalex.org/W2141345935","https://openalex.org/W2150042021","https://openalex.org/W2153859117","https://openalex.org/W2160823654","https://openalex.org/W2167775755","https://openalex.org/W2169096324","https://openalex.org/W4231905827","https://openalex.org/W4298011152","https://openalex.org/W6683394555"],"related_works":["https://openalex.org/W853533475","https://openalex.org/W364924225","https://openalex.org/W60393894","https://openalex.org/W2095703739","https://openalex.org/W2325117947","https://openalex.org/W628161287","https://openalex.org/W2606047588","https://openalex.org/W158833317","https://openalex.org/W794031490","https://openalex.org/W2349909378"],"abstract_inverted_index":{"Complex":[0],"synchronous":[1],"digital":[2,81],"systems":[3,82],"can":[4],"be":[5],"implemented":[6],"on":[7,83],"FPGAs":[8],"(Field":[9],"Programmable":[10],"Gate":[11],"Arrays),":[12],"but":[13],"due":[14],"to":[15,34,46,53],"the":[16,38,43,47,59,66,89,97,105,112,124,127],"global":[17],"clock,":[18],"might":[19],"have":[20],"problems":[21,44],"with":[22],"clock":[23],"skew,":[24],"performance":[25],"degradation":[26],"and":[27],"increased":[28],"of":[29,68,91,99,126],"power":[30],"consumed.":[31],"An":[32],"alternative":[33],"these":[35],"designs":[36],"is":[37,51,122],"asynchronous":[39,55,69,80,100,106],"paradigm":[40,92],"that":[41,78],"solves":[42],"related":[45],"clock.":[48],"However":[49],"it":[50,121],"difficult":[52],"design":[54],"circuits,":[56],"especially":[57],"in":[58,65],"FPGA":[60],"platform.":[61],"This":[62],"work":[63],"presents":[64],"style":[67],"FSM":[70,107],"(finite":[71],"state":[72,114],"machine)":[73],"+":[74],"data-path":[75],"a":[76,118],"method":[77,87,103],"implements":[79],"FPGAs.":[84],"The":[85],"proposed":[86,128],"uses":[88],"tools":[90],"synchronous,":[93],"thus":[94],"synthesizes":[95,104],"without":[96],"knowledge":[98],"logic.":[101],"Our":[102],"by":[108],"direct":[109],"mapping":[110],"from":[111],"conventional":[113],"transition":[115],"graph.":[116],"Through":[117],"case":[119],"study,":[120],"shown":[123],"simplicity":[125],"methodology.":[129]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2020,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}