{"id":"https://openalex.org/W2067709990","doi":"https://doi.org/10.1109/reconfig.2013.6732275","title":"Design and implementation of a modular, low latency, fault-aware, FPGA-based network interface","display_name":"Design and implementation of a modular, low latency, fault-aware, FPGA-based network interface","publication_year":2013,"publication_date":"2013-12-01","ids":{"openalex":"https://openalex.org/W2067709990","doi":"https://doi.org/10.1109/reconfig.2013.6732275","mag":"2067709990"},"language":"en","primary_location":{"id":"doi:10.1109/reconfig.2013.6732275","is_oa":false,"landing_page_url":"https://doi.org/10.1109/reconfig.2013.6732275","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 International Conference on Reconfigurable Computing and FPGAs (ReConFig)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5047080284","display_name":"Roberto Ammendola","orcid":"https://orcid.org/0000-0003-4501-3289"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Roberto Ammendola","raw_affiliation_strings":["INFN Roma \u201cTor Vergata\u201d","INFN Roma \"Tor Vergata\""],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"INFN Roma \u201cTor Vergata\u201d","institution_ids":[]},{"raw_affiliation_string":"INFN Roma \"Tor Vergata\"","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5107243926","display_name":"A. Biagioni","orcid":"https://orcid.org/0000-0001-5820-1209"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Andrea Biagionil","raw_affiliation_strings":["INFN Roma \u201cSapienza\u201d","INFN Roma \"Sapienza\""],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"INFN Roma \u201cSapienza\u201d","institution_ids":[]},{"raw_affiliation_string":"INFN Roma \"Sapienza\"","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5044124783","display_name":"Ottorino Frezza","orcid":"https://orcid.org/0000-0001-8277-1877"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Ottorino Frezza","raw_affiliation_strings":["INFN Roma \u201cSapienza\u201d","INFN Roma \"Sapienza\""],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"INFN Roma \u201cSapienza\u201d","institution_ids":[]},{"raw_affiliation_string":"INFN Roma \"Sapienza\"","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5069985222","display_name":"Francesca Lo Cicero","orcid":"https://orcid.org/0000-0002-9904-2619"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Francesca Lo Cicero","raw_affiliation_strings":["INFN Roma \u201cSapienza\u201d","INFN Roma \"Sapienza\""],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"INFN Roma \u201cSapienza\u201d","institution_ids":[]},{"raw_affiliation_string":"INFN Roma \"Sapienza\"","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5107247182","display_name":"A. Lonardo","orcid":"https://orcid.org/0000-0002-5909-6508"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Alessandro Lonardo","raw_affiliation_strings":["INFN Roma \u201cSapienza\u201d","INFN Roma \"Sapienza\""],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"INFN Roma \u201cSapienza\u201d","institution_ids":[]},{"raw_affiliation_string":"INFN Roma \"Sapienza\"","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5069161544","display_name":"Pier Stanislao Paolucci","orcid":"https://orcid.org/0000-0003-1937-6086"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Pier Stanislao Paolucci","raw_affiliation_strings":["INFN Roma \u201cSapienza\u201d","INFN Roma \"Sapienza\""],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"INFN Roma \u201cSapienza\u201d","institution_ids":[]},{"raw_affiliation_string":"INFN Roma \"Sapienza\"","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5107847317","display_name":"Davide Rossetti","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Davide Rossetti","raw_affiliation_strings":["INFN Roma \u201cSapienza\u201d","INFN Roma \"Sapienza\""],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"INFN Roma \u201cSapienza\u201d","institution_ids":[]},{"raw_affiliation_string":"INFN Roma \"Sapienza\"","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5034039729","display_name":"Francesco Simula","orcid":"https://orcid.org/0000-0002-7955-1491"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Francesco Simula","raw_affiliation_strings":["INFN Roma \u201cSapienza\u201d","INFN Roma \"Sapienza\""],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"INFN Roma \u201cSapienza\u201d","institution_ids":[]},{"raw_affiliation_string":"INFN Roma \"Sapienza\"","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5041037171","display_name":"Laura Tosoratto","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Laura Tosoratto","raw_affiliation_strings":["INFN Roma \u201cSapienza\u201d","INFN Roma \"Sapienza\""],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"INFN Roma \u201cSapienza\u201d","institution_ids":[]},{"raw_affiliation_string":"INFN Roma \"Sapienza\"","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5038787613","display_name":"P. Vicini","orcid":"https://orcid.org/0000-0002-4379-4563"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Piero Vicini","raw_affiliation_strings":["INFN Roma \u201cSapienza\u201d","INFN Roma \"Sapienza\""],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"INFN Roma \u201cSapienza\u201d","institution_ids":[]},{"raw_affiliation_string":"INFN Roma \"Sapienza\"","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9973999857902527,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9973000288009644,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/pci-express","display_name":"PCI Express","score":0.8869781494140625},{"id":"https://openalex.org/keywords/remote-direct-memory-access","display_name":"Remote direct memory access","score":0.8276216983795166},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7395519018173218},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6534131169319153},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5391926765441895},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.5207352638244629},{"id":"https://openalex.org/keywords/modular-design","display_name":"Modular design","score":0.4920329749584198},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.45958179235458374},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.44989341497421265},{"id":"https://openalex.org/keywords/network-interface","display_name":"Network interface","score":0.41754353046417236},{"id":"https://openalex.org/keywords/fault-tolerance","display_name":"Fault tolerance","score":0.41054511070251465},{"id":"https://openalex.org/keywords/ethernet","display_name":"Ethernet","score":0.2048656940460205}],"concepts":[{"id":"https://openalex.org/C64270927","wikidata":"https://www.wikidata.org/wiki/Q206924","display_name":"PCI Express","level":3,"score":0.8869781494140625},{"id":"https://openalex.org/C130795937","wikidata":"https://www.wikidata.org/wiki/Q2561570","display_name":"Remote direct memory access","level":2,"score":0.8276216983795166},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7395519018173218},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6534131169319153},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5391926765441895},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.5207352638244629},{"id":"https://openalex.org/C101468663","wikidata":"https://www.wikidata.org/wiki/Q1620158","display_name":"Modular design","level":2,"score":0.4920329749584198},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.45958179235458374},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.44989341497421265},{"id":"https://openalex.org/C103987645","wikidata":"https://www.wikidata.org/wiki/Q985806","display_name":"Network interface","level":3,"score":0.41754353046417236},{"id":"https://openalex.org/C63540848","wikidata":"https://www.wikidata.org/wiki/Q3140932","display_name":"Fault tolerance","level":2,"score":0.41054511070251465},{"id":"https://openalex.org/C172173386","wikidata":"https://www.wikidata.org/wiki/Q79984","display_name":"Ethernet","level":2,"score":0.2048656940460205},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/reconfig.2013.6732275","is_oa":false,"landing_page_url":"https://doi.org/10.1109/reconfig.2013.6732275","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 International Conference on Reconfigurable Computing and FPGAs (ReConFig)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5099999904632568,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320327843","display_name":"Istituto Nazionale di Fisica Nucleare","ror":null}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1610483991","https://openalex.org/W1988756252","https://openalex.org/W1994993486","https://openalex.org/W2002441714","https://openalex.org/W2005111477","https://openalex.org/W2077236754","https://openalex.org/W2144399876","https://openalex.org/W2168934541","https://openalex.org/W3101836229","https://openalex.org/W4299805602","https://openalex.org/W6649116730","https://openalex.org/W6785865270"],"related_works":["https://openalex.org/W3135214639","https://openalex.org/W2197138596","https://openalex.org/W2248641188","https://openalex.org/W1901618855","https://openalex.org/W4309997664","https://openalex.org/W3105798355","https://openalex.org/W2937592512","https://openalex.org/W3034923428","https://openalex.org/W4311118888","https://openalex.org/W3162045814"],"abstract_inverted_index":{"We":[0,34],"describe":[1],"the":[2,12,17,44,49,52,61,78,84,97,99,102,122,127,138,142],"hands-on":[3],"experience":[4],"in":[5,121],"developing":[6],"a":[7,30,64,68,72,87,114,118,132],"network-centric":[8],"IP":[9,74,91,104],"core":[10,103],"supporting":[11],"RDMA":[13,65],"protocol":[14,80],"which":[15],"is":[16],"engine":[18,66],"of":[19,57,63,81,86,126,131,141],"an":[20],"FPGA-based":[21],"PCIe":[22,147],"NIC":[23,50],"targeted":[24],"for":[25,157],"GPU-accelerated":[26],"HPC":[27],"clusters":[28],"with":[29,67,152],"3D-toroidal":[31],"network":[32],"topology.":[33],"report":[35],"on":[36],"different":[37],"development":[38,62],"areas":[39],"related":[40],"to":[41,47,51,96,101,105],"our":[42,158],"IP:":[43],"optimizations":[45],"required":[46],"evolve":[48],"current":[53],"performance":[54],"level":[55,129],"(highlights":[56],"this":[58],"work":[59],"include":[60],"dedicated":[69],"translation-lookaside-buffer":[70],"and":[71,117],"first-of-its-kind":[73],"module":[75],"that":[76,92],"exploits":[77],"peer-to-peer":[79],"NVIDIA":[82],"GPUs);":[83],"addition":[85],"component":[88],"called":[89,111],"LO|FA|MO":[90],"provides":[93],"systemic":[94],"fault-awareness":[95],"network;":[98],"modifications":[100],"turn":[106],"it":[107],"into":[108,136],"low-latency":[109],"interface":[110],"NaNet":[112],"between":[113],"read-out":[115],"board":[116],"GPU":[119],"farm":[120],"data":[123],"acquisition":[124],"system":[125],"low":[128],"trigger":[130],"particle-physics":[133],"experiment.":[134],"Taking":[135],"account":[137],"forecast":[139],"evolution":[140],"FPGA":[143],"platform":[144],"(28":[145],"nm,":[146],"Gen3,":[148],"etc.),":[149],"we":[150,155],"conclude":[151],"future":[153],"directions":[154],"envision":[156],"IP.":[159]},"counts_by_year":[{"year":2018,"cited_by_count":1},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":2}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}