{"id":"https://openalex.org/W2094825347","doi":"https://doi.org/10.1109/reconfig.2012.6416785","title":"Robustness of different TMR granularities in shared wishbone architectures on SRAM FPGA","display_name":"Robustness of different TMR granularities in shared wishbone architectures on SRAM FPGA","publication_year":2012,"publication_date":"2012-12-01","ids":{"openalex":"https://openalex.org/W2094825347","doi":"https://doi.org/10.1109/reconfig.2012.6416785","mag":"2094825347"},"language":"en","primary_location":{"id":"doi:10.1109/reconfig.2012.6416785","is_oa":false,"landing_page_url":"https://doi.org/10.1109/reconfig.2012.6416785","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 International Conference on Reconfigurable Computing and FPGAs","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5034117354","display_name":"Uli Kretzschmar","orcid":null},"institutions":[{"id":"https://openalex.org/I169108374","display_name":"University of the Basque Country","ror":"https://ror.org/000xsnr85","country_code":"ES","type":"education","lineage":["https://openalex.org/I169108374"]}],"countries":["ES"],"is_corresponding":true,"raw_author_name":"U. Kretzschmar","raw_affiliation_strings":["Department of Electronics and Telecommunications, University of the Basque Country UPV/EHU, Bilbao, Spain","Department of Electronics And Telecommunications, University of the Basque Country UPV/EHU, Bilbao, Spain"],"affiliations":[{"raw_affiliation_string":"Department of Electronics and Telecommunications, University of the Basque Country UPV/EHU, Bilbao, Spain","institution_ids":["https://openalex.org/I169108374"]},{"raw_affiliation_string":"Department of Electronics And Telecommunications, University of the Basque Country UPV/EHU, Bilbao, Spain","institution_ids":["https://openalex.org/I169108374"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5030280508","display_name":"Armando Astarloa","orcid":"https://orcid.org/0000-0002-6330-1922"},"institutions":[{"id":"https://openalex.org/I169108374","display_name":"University of the Basque Country","ror":"https://ror.org/000xsnr85","country_code":"ES","type":"education","lineage":["https://openalex.org/I169108374"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"A. Astarloa","raw_affiliation_strings":["Department of Electronics and Telecommunications, University of the Basque Country UPV/EHU, Bilbao, Spain","Department of Electronics And Telecommunications, University of the Basque Country UPV/EHU, Bilbao, Spain"],"affiliations":[{"raw_affiliation_string":"Department of Electronics and Telecommunications, University of the Basque Country UPV/EHU, Bilbao, Spain","institution_ids":["https://openalex.org/I169108374"]},{"raw_affiliation_string":"Department of Electronics And Telecommunications, University of the Basque Country UPV/EHU, Bilbao, Spain","institution_ids":["https://openalex.org/I169108374"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5026679122","display_name":"Jes\u00fas L\u00e1zaro","orcid":"https://orcid.org/0000-0002-7483-3609"},"institutions":[{"id":"https://openalex.org/I169108374","display_name":"University of the Basque Country","ror":"https://ror.org/000xsnr85","country_code":"ES","type":"education","lineage":["https://openalex.org/I169108374"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"J. Lazaro","raw_affiliation_strings":["Department of Electronics and Telecommunications, University of the Basque Country UPV/EHU, Bilbao, Spain","Department of Electronics And Telecommunications, University of the Basque Country UPV/EHU, Bilbao, Spain"],"affiliations":[{"raw_affiliation_string":"Department of Electronics and Telecommunications, University of the Basque Country UPV/EHU, Bilbao, Spain","institution_ids":["https://openalex.org/I169108374"]},{"raw_affiliation_string":"Department of Electronics And Telecommunications, University of the Basque Country UPV/EHU, Bilbao, Spain","institution_ids":["https://openalex.org/I169108374"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5061237445","display_name":"M. Garay","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"M. Garay","raw_affiliation_strings":["TELECOM Unit, TECNALIA RESEARCH & INNOVATION, Zamudio, Spain"],"affiliations":[{"raw_affiliation_string":"TELECOM Unit, TECNALIA RESEARCH & INNOVATION, Zamudio, Spain","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5017326471","display_name":"Javier Del Ser","orcid":"https://orcid.org/0000-0002-1260-9775"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"J. Del Ser","raw_affiliation_strings":["TELECOM Unit, TECNALIA RESEARCH & INNOVATION, Zamudio, Spain"],"affiliations":[{"raw_affiliation_string":"TELECOM Unit, TECNALIA RESEARCH & INNOVATION, Zamudio, Spain","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5034117354"],"corresponding_institution_ids":["https://openalex.org/I169108374"],"apc_list":null,"apc_paid":null,"fwci":1.7835,"has_fulltext":false,"cited_by_count":14,"citation_normalized_percentile":{"value":0.85031469,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8485969305038452},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7425705194473267},{"id":"https://openalex.org/keywords/robustness","display_name":"Robustness (evolution)","score":0.7306469678878784},{"id":"https://openalex.org/keywords/triple-modular-redundancy","display_name":"Triple modular redundancy","score":0.6903183460235596},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.571060299873352},{"id":"https://openalex.org/keywords/bitstream","display_name":"Bitstream","score":0.5258144736289978},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.5066083669662476},{"id":"https://openalex.org/keywords/redundancy","display_name":"Redundancy (engineering)","score":0.4708870053291321},{"id":"https://openalex.org/keywords/virtex","display_name":"Virtex","score":0.4521104395389557},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.41889306902885437},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3726420998573303},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3418433666229248},{"id":"https://openalex.org/keywords/decoding-methods","display_name":"Decoding methods","score":0.2728370130062103},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.10993686318397522},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.08546942472457886}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8485969305038452},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7425705194473267},{"id":"https://openalex.org/C63479239","wikidata":"https://www.wikidata.org/wiki/Q7353546","display_name":"Robustness (evolution)","level":3,"score":0.7306469678878784},{"id":"https://openalex.org/C196371267","wikidata":"https://www.wikidata.org/wiki/Q3998979","display_name":"Triple modular redundancy","level":3,"score":0.6903183460235596},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.571060299873352},{"id":"https://openalex.org/C136695289","wikidata":"https://www.wikidata.org/wiki/Q415568","display_name":"Bitstream","level":3,"score":0.5258144736289978},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.5066083669662476},{"id":"https://openalex.org/C152124472","wikidata":"https://www.wikidata.org/wiki/Q1204361","display_name":"Redundancy (engineering)","level":2,"score":0.4708870053291321},{"id":"https://openalex.org/C2777674469","wikidata":"https://www.wikidata.org/wiki/Q20741011","display_name":"Virtex","level":3,"score":0.4521104395389557},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.41889306902885437},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3726420998573303},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3418433666229248},{"id":"https://openalex.org/C57273362","wikidata":"https://www.wikidata.org/wiki/Q576722","display_name":"Decoding methods","level":2,"score":0.2728370130062103},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.10993686318397522},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.08546942472457886},{"id":"https://openalex.org/C104317684","wikidata":"https://www.wikidata.org/wiki/Q7187","display_name":"Gene","level":2,"score":0.0},{"id":"https://openalex.org/C55493867","wikidata":"https://www.wikidata.org/wiki/Q7094","display_name":"Biochemistry","level":1,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/reconfig.2012.6416785","is_oa":false,"landing_page_url":"https://doi.org/10.1109/reconfig.2012.6416785","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 International Conference on Reconfigurable Computing and FPGAs","raw_type":"proceedings-article"},{"id":"pmh:oai:dsp.tecnalia.com:11556/1933","is_oa":false,"landing_page_url":"https://hdl.handle.net/11556/1933","pdf_url":null,"source":{"id":"https://openalex.org/S4306402037","display_name":"TECNALIA Publications (Fundaci\u00f3n TECNALIA Research & Innovation)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I4210113430","host_organization_name":"Tecnalia","host_organization_lineage":["https://openalex.org/I4210113430"],"host_organization_lineage_names":[],"type":"repository"},"license":"public-domain","license_id":"https://openalex.org/licenses/public-domain","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"conference output"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320321705","display_name":"Eusko Jaurlaritza","ror":"https://ror.org/00pz2fp31"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W1530384521","https://openalex.org/W1625650886","https://openalex.org/W2134743663","https://openalex.org/W2153224608","https://openalex.org/W2163131937","https://openalex.org/W2169203378","https://openalex.org/W2170171948","https://openalex.org/W4251792943"],"related_works":["https://openalex.org/W58658798","https://openalex.org/W3114375939","https://openalex.org/W2544043553","https://openalex.org/W3008821054","https://openalex.org/W2797678940","https://openalex.org/W1587494897","https://openalex.org/W2759696718","https://openalex.org/W2385174725","https://openalex.org/W2169674017","https://openalex.org/W2359816675"],"abstract_inverted_index":{"Triple":[0],"Module":[1],"Redundancy":[2],"(TMR)":[3],"is":[4,63,86],"a":[5,44,47,52,66,104],"popular":[6],"technique":[7],"for":[8,16,28,92],"protecting":[9],"critical":[10],"FPGA":[11,69],"designs.":[12],"Although":[13],"automatic":[14],"tools":[15],"TMR":[17,40,49,110],"generation":[18],"mostly":[19],"use":[20],"triplication":[21],"on":[22,39,43,65,100],"flip-flop":[23],"level,":[24],"designers":[25],"may":[26],"opt":[27],"different":[29,37,61],"approaches.":[30],"This":[31],"work":[32],"analyses":[33],"the":[34,75,93,96,101],"impact":[35],"of":[36,51,59,95,107],"granularities":[38],"architectures":[41,111],"based":[42],"coarse-":[45],"and":[46],"medium-grained":[48],"implementation":[50],"shared":[53],"Wishbone":[54],"interconnection.":[55],"The":[56],"actual":[57],"robustness":[58,97],"these":[60],"implementations":[62],"measured":[64],"Xilinx":[67],"Virtex-5":[68],"by":[70],"using":[71],"error":[72],"injection":[73],"into":[74],"configuration":[76],"bitstream.":[77],"A":[78],"specialized":[79],"test":[80],"setup":[81],"comprising":[82],"two":[83],"FPGAs":[84],"boards":[85],"introduced":[87],"so":[88],"as":[89],"to":[90],"allow":[91],"execution":[94],"testing.":[98],"Based":[99],"coarse-grained":[102],"architecture,":[103],"fine":[105],"categorization":[106],"errors":[108],"in":[109],"can":[112],"be":[113],"obtained.":[114]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2019,"cited_by_count":2},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":3},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":3}],"updated_date":"2026-03-16T09:10:04.655348","created_date":"2025-10-10T00:00:00"}