{"id":"https://openalex.org/W2167916762","doi":"https://doi.org/10.1109/reconfig.2012.6416747","title":"Exploring hardware work queue support for lightweight threads in MPSoCs","display_name":"Exploring hardware work queue support for lightweight threads in MPSoCs","publication_year":2012,"publication_date":"2012-12-01","ids":{"openalex":"https://openalex.org/W2167916762","doi":"https://doi.org/10.1109/reconfig.2012.6416747","mag":"2167916762"},"language":"en","primary_location":{"id":"doi:10.1109/reconfig.2012.6416747","is_oa":false,"landing_page_url":"https://doi.org/10.1109/reconfig.2012.6416747","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 International Conference on Reconfigurable Computing and FPGAs","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101769895","display_name":"Rahul Sharma","orcid":"https://orcid.org/0000-0001-7527-4653"},"institutions":[{"id":"https://openalex.org/I102149020","display_name":"University of North Carolina at Charlotte","ror":"https://ror.org/04dawnj30","country_code":"US","type":"education","lineage":["https://openalex.org/I102149020"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Rahul R Sharma","raw_affiliation_strings":["Reconfigurable Computing Systems Laboratory, University of North Carolina, Charlotte, USA"],"affiliations":[{"raw_affiliation_string":"Reconfigurable Computing Systems Laboratory, University of North Carolina, Charlotte, USA","institution_ids":["https://openalex.org/I102149020"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5004731428","display_name":"Yamuna Rajasekhar","orcid":null},"institutions":[{"id":"https://openalex.org/I102149020","display_name":"University of North Carolina at Charlotte","ror":"https://ror.org/04dawnj30","country_code":"US","type":"education","lineage":["https://openalex.org/I102149020"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yamuna Rajasekhar","raw_affiliation_strings":["Reconfigurable Computing Systems Laboratory, University of North Carolina, Charlotte, USA"],"affiliations":[{"raw_affiliation_string":"Reconfigurable Computing Systems Laboratory, University of North Carolina, Charlotte, USA","institution_ids":["https://openalex.org/I102149020"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5106082786","display_name":"Ron Sass","orcid":null},"institutions":[{"id":"https://openalex.org/I102149020","display_name":"University of North Carolina at Charlotte","ror":"https://ror.org/04dawnj30","country_code":"US","type":"education","lineage":["https://openalex.org/I102149020"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ron Sass","raw_affiliation_strings":["Reconfigurable Computing Systems Laboratory, University of North Carolina, Charlotte, USA"],"affiliations":[{"raw_affiliation_string":"Reconfigurable Computing Systems Laboratory, University of North Carolina, Charlotte, USA","institution_ids":["https://openalex.org/I102149020"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5101769895"],"corresponding_institution_ids":["https://openalex.org/I102149020"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.17575417,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"23","issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10715","display_name":"Distributed and Parallel Computing Systems","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8477796912193298},{"id":"https://openalex.org/keywords/bottleneck","display_name":"Bottleneck","score":0.6441354751586914},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5437245965003967},{"id":"https://openalex.org/keywords/thread","display_name":"Thread (computing)","score":0.5290274620056152},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.525137186050415},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.49802064895629883},{"id":"https://openalex.org/keywords/massively-parallel","display_name":"Massively parallel","score":0.479262113571167},{"id":"https://openalex.org/keywords/direct-memory-access","display_name":"Direct memory access","score":0.4555266499519348},{"id":"https://openalex.org/keywords/queue","display_name":"Queue","score":0.45171666145324707},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.4514042139053345},{"id":"https://openalex.org/keywords/task-parallelism","display_name":"Task parallelism","score":0.44010451436042786},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.3761112093925476},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3229016065597534},{"id":"https://openalex.org/keywords/parallelism","display_name":"Parallelism (grammar)","score":0.205402672290802}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8477796912193298},{"id":"https://openalex.org/C2780513914","wikidata":"https://www.wikidata.org/wiki/Q18210350","display_name":"Bottleneck","level":2,"score":0.6441354751586914},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5437245965003967},{"id":"https://openalex.org/C138101251","wikidata":"https://www.wikidata.org/wiki/Q213092","display_name":"Thread (computing)","level":2,"score":0.5290274620056152},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.525137186050415},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.49802064895629883},{"id":"https://openalex.org/C190475519","wikidata":"https://www.wikidata.org/wiki/Q544384","display_name":"Massively parallel","level":2,"score":0.479262113571167},{"id":"https://openalex.org/C37724790","wikidata":"https://www.wikidata.org/wiki/Q210813","display_name":"Direct memory access","level":3,"score":0.4555266499519348},{"id":"https://openalex.org/C160403385","wikidata":"https://www.wikidata.org/wiki/Q220543","display_name":"Queue","level":2,"score":0.45171666145324707},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.4514042139053345},{"id":"https://openalex.org/C42992933","wikidata":"https://www.wikidata.org/wiki/Q691169","display_name":"Task parallelism","level":3,"score":0.44010451436042786},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.3761112093925476},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3229016065597534},{"id":"https://openalex.org/C2781172179","wikidata":"https://www.wikidata.org/wiki/Q853109","display_name":"Parallelism (grammar)","level":2,"score":0.205402672290802},{"id":"https://openalex.org/C2776175482","wikidata":"https://www.wikidata.org/wiki/Q1195816","display_name":"Transfer (computing)","level":2,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/reconfig.2012.6416747","is_oa":false,"landing_page_url":"https://doi.org/10.1109/reconfig.2012.6416747","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 International Conference on Reconfigurable Computing and FPGAs","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.44999998807907104}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":24,"referenced_works":["https://openalex.org/W160921400","https://openalex.org/W1990383399","https://openalex.org/W2012381119","https://openalex.org/W2032401773","https://openalex.org/W2072725684","https://openalex.org/W2090409324","https://openalex.org/W2096791627","https://openalex.org/W2107194324","https://openalex.org/W2109065830","https://openalex.org/W2115747685","https://openalex.org/W2130819328","https://openalex.org/W2133394135","https://openalex.org/W2135063076","https://openalex.org/W2142759683","https://openalex.org/W2149590159","https://openalex.org/W2149663533","https://openalex.org/W2160701576","https://openalex.org/W3016205154","https://openalex.org/W4205190765","https://openalex.org/W4234858060","https://openalex.org/W4241166746","https://openalex.org/W4242946001","https://openalex.org/W4285719527","https://openalex.org/W6606521517"],"related_works":["https://openalex.org/W1970433854","https://openalex.org/W2023867642","https://openalex.org/W1905852083","https://openalex.org/W2109126387","https://openalex.org/W2185482126","https://openalex.org/W1981872744","https://openalex.org/W4248099758","https://openalex.org/W2126866131","https://openalex.org/W4241547419","https://openalex.org/W2104702637"],"abstract_inverted_index":{"Fine-grain":[0],"thread":[1],"parallelism":[2],"using":[3],"task":[4],"based":[5,69],"programming":[6],"models":[7],"are":[8,28,95],"a":[9,53,62,67,87,91],"new":[10],"trend":[11],"in":[12,61],"achieving":[13],"massively":[14],"parallel":[15],"computations.":[16],"Often,":[17],"software":[18,111],"pre-fetching":[19,70],"and":[20,50,71,90,108],"queuing":[21,72],"mechanisms":[22],"for":[23],"managing":[24],"these":[25],"dynamic":[26],"environments":[27],"inadequate,":[29],"failing":[30],"to":[31,58,102],"keep":[32,59],"the":[33,40,43,77,100,110],"processor":[34,89],"cores":[35,60],"busy":[36,63],"with":[37,86],"computation.":[38],"At":[39],"same":[41],"time,":[42],"CPU-memory":[44],"performance":[45],"gap":[46],"is":[47],"getting":[48],"worse":[49],"this":[51],"puts":[52],"strain":[54],"on":[55,104],"memory":[56,106],"subsystem":[57],"state.":[64],"We":[65],"describe":[66],"hardware":[68,98],"mechanism":[73],"aimed":[74],"at":[75],"assisting":[76],"over-subscription":[78],"of":[79],"very":[80],"lightweight":[81],"threads":[82],"per":[83],"core.":[84],"Experiments":[85],"soft":[88],"reconfigurable":[92],"accelerator":[93],"core":[94],"reported.":[96],"The":[97],"demonstrates":[99],"ability":[101],"block":[103],"out-of-order":[105],"transactions":[107],"alleviates":[109],"bottleneck.":[112]},"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}