{"id":"https://openalex.org/W2810100363","doi":"https://doi.org/10.1109/rait.2018.8389016","title":"Design of low power RRAM cell using CNFET","display_name":"Design of low power RRAM cell using CNFET","publication_year":2018,"publication_date":"2018-03-01","ids":{"openalex":"https://openalex.org/W2810100363","doi":"https://doi.org/10.1109/rait.2018.8389016","mag":"2810100363"},"language":"en","primary_location":{"id":"doi:10.1109/rait.2018.8389016","is_oa":false,"landing_page_url":"https://doi.org/10.1109/rait.2018.8389016","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 4th International Conference on Recent Advances in Information Technology (RAIT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5028499988","display_name":"Srinithya Nagiri","orcid":null},"institutions":[{"id":"https://openalex.org/I115715567","display_name":"Birla Institute of Technology, Mesra","ror":"https://ror.org/028vtqb15","country_code":"IN","type":"education","lineage":["https://openalex.org/I115715567"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Srinithya Nagiri","raw_affiliation_strings":["Birla Institute of Technology, Ranchi, Jharkhand, IN"],"affiliations":[{"raw_affiliation_string":"Birla Institute of Technology, Ranchi, Jharkhand, IN","institution_ids":["https://openalex.org/I115715567"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5005148800","display_name":"Sananya Majumder","orcid":null},"institutions":[{"id":"https://openalex.org/I115715567","display_name":"Birla Institute of Technology, Mesra","ror":"https://ror.org/028vtqb15","country_code":"IN","type":"education","lineage":["https://openalex.org/I115715567"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Sananya Majumder","raw_affiliation_strings":["Birla Institute of Technology, Ranchi, Jharkhand, IN"],"affiliations":[{"raw_affiliation_string":"Birla Institute of Technology, Ranchi, Jharkhand, IN","institution_ids":["https://openalex.org/I115715567"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5029278888","display_name":"Riya","orcid":null},"institutions":[{"id":"https://openalex.org/I115715567","display_name":"Birla Institute of Technology, Mesra","ror":"https://ror.org/028vtqb15","country_code":"IN","type":"education","lineage":["https://openalex.org/I115715567"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Riya","raw_affiliation_strings":["Birla Institute of Technology, Ranchi, Jharkhand, IN"],"affiliations":[{"raw_affiliation_string":"Birla Institute of Technology, Ranchi, Jharkhand, IN","institution_ids":["https://openalex.org/I115715567"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5043563773","display_name":"Aminul Islam","orcid":"https://orcid.org/0000-0002-6366-3915"},"institutions":[{"id":"https://openalex.org/I115715567","display_name":"Birla Institute of Technology, Mesra","ror":"https://ror.org/028vtqb15","country_code":"IN","type":"education","lineage":["https://openalex.org/I115715567"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Aminul Islam","raw_affiliation_strings":["Birla Institute of Technology, Ranchi, Jharkhand, IN"],"affiliations":[{"raw_affiliation_string":"Birla Institute of Technology, Ranchi, Jharkhand, IN","institution_ids":["https://openalex.org/I115715567"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5028499988"],"corresponding_institution_ids":["https://openalex.org/I115715567"],"apc_list":null,"apc_paid":null,"fwci":0.1288,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.46836038,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11601","display_name":"Neuroscience and Neural Engineering","score":0.9961000084877014,"subfield":{"id":"https://openalex.org/subfields/2804","display_name":"Cellular and Molecular Neuroscience"},"field":{"id":"https://openalex.org/fields/28","display_name":"Neuroscience"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/resistive-random-access-memory","display_name":"Resistive random-access memory","score":0.9564878940582275},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.5900160670280457},{"id":"https://openalex.org/keywords/memory-cell","display_name":"Memory cell","score":0.5524671077728271},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.524531900882721},{"id":"https://openalex.org/keywords/non-volatile-memory","display_name":"Non-volatile memory","score":0.47740331292152405},{"id":"https://openalex.org/keywords/memristor","display_name":"Memristor","score":0.4538896381855011},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.38519713282585144},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.25410282611846924},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.22401615977287292},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.16069695353507996},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.11229333281517029},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.06950822472572327},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.054885536432266235}],"concepts":[{"id":"https://openalex.org/C182019814","wikidata":"https://www.wikidata.org/wiki/Q1143830","display_name":"Resistive random-access memory","level":3,"score":0.9564878940582275},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.5900160670280457},{"id":"https://openalex.org/C2776638159","wikidata":"https://www.wikidata.org/wiki/Q18343761","display_name":"Memory cell","level":4,"score":0.5524671077728271},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.524531900882721},{"id":"https://openalex.org/C177950962","wikidata":"https://www.wikidata.org/wiki/Q10997658","display_name":"Non-volatile memory","level":2,"score":0.47740331292152405},{"id":"https://openalex.org/C150072547","wikidata":"https://www.wikidata.org/wiki/Q212923","display_name":"Memristor","level":2,"score":0.4538896381855011},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.38519713282585144},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.25410282611846924},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.22401615977287292},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.16069695353507996},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.11229333281517029},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.06950822472572327},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.054885536432266235},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/rait.2018.8389016","is_oa":false,"landing_page_url":"https://doi.org/10.1109/rait.2018.8389016","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 4th International Conference on Recent Advances in Information Technology (RAIT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.8899999856948853,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W2061255969","https://openalex.org/W2063483597","https://openalex.org/W2103684670","https://openalex.org/W2162651880","https://openalex.org/W2164354609","https://openalex.org/W2168734154","https://openalex.org/W2399135913","https://openalex.org/W2521200950","https://openalex.org/W2586355270"],"related_works":["https://openalex.org/W2076211355","https://openalex.org/W2533127403","https://openalex.org/W2007070351","https://openalex.org/W2033811947","https://openalex.org/W2183989414","https://openalex.org/W2106343578","https://openalex.org/W1551399929","https://openalex.org/W2410132916","https://openalex.org/W989761102","https://openalex.org/W2162174949"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,22,78],"CNFET":[4],"based":[5],"novel":[6],"RRAM":[7,16,38,43,49,82],"cell":[8,17,39,44,50,72,83],"using":[9],"memristor":[10],"as":[11],"memory":[12],"element.":[13],"The":[14,47],"proposed":[15,37,48],"is":[18,27,77,90],"designed":[19],"in":[20],"such":[21],"way":[23],"that":[24],"half-select":[25,79],"issue":[26],"resolved.":[28],"Simulation":[29],"results":[30],"of":[31,35,65],"critical":[32],"design":[33],"metrics":[34],"the":[36],"and":[40,88],"previous":[41],"2T2M":[42,71],"are":[45],"compared.":[46],"achieves":[51],"6.13x":[52],"lower":[53,59],"read":[54,86],"delay":[55],"along":[56],"with":[57,84],"33x":[58],"hold":[60],"power":[61,67,92],"due":[62],"to":[63],"use":[64],"MTCMOS":[66],"reduction":[68],"technique":[69],"than":[70],"at":[73],"nominal":[74],"VDD.":[75],"It":[76],"free":[80],"non-volatile":[81],"faster":[85],"operation":[87],"it":[89],"also":[91],"efficient.":[93]},"counts_by_year":[{"year":2019,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
