{"id":"https://openalex.org/W2810613542","doi":"https://doi.org/10.1109/rait.2018.8388985","title":"Enhancing the lifetime of STT-RAM with MRU replacement algorithm","display_name":"Enhancing the lifetime of STT-RAM with MRU replacement algorithm","publication_year":2018,"publication_date":"2018-03-01","ids":{"openalex":"https://openalex.org/W2810613542","doi":"https://doi.org/10.1109/rait.2018.8388985","mag":"2810613542"},"language":"en","primary_location":{"id":"doi:10.1109/rait.2018.8388985","is_oa":false,"landing_page_url":"https://doi.org/10.1109/rait.2018.8388985","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 4th International Conference on Recent Advances in Information Technology (RAIT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5040217125","display_name":"Bhukya Krishna Priya","orcid":"https://orcid.org/0000-0002-9888-3125"},"institutions":[{"id":"https://openalex.org/I122964287","display_name":"National Institute of Technology Tiruchirappalli","ror":"https://ror.org/047x65e68","country_code":"IN","type":"education","lineage":["https://openalex.org/I122964287"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Bhukya Krishna Priya","raw_affiliation_strings":["Computer science Engineering, National Institute of Technology, Tiruchirappalli, India"],"affiliations":[{"raw_affiliation_string":"Computer science Engineering, National Institute of Technology, Tiruchirappalli, India","institution_ids":["https://openalex.org/I122964287"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110628606","display_name":"Sampath Kumar","orcid":null},"institutions":[{"id":"https://openalex.org/I122964287","display_name":"National Institute of Technology Tiruchirappalli","ror":"https://ror.org/047x65e68","country_code":"IN","type":"education","lineage":["https://openalex.org/I122964287"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Sampath Kumar","raw_affiliation_strings":["Computer science Engineering, National Institute of Technology, Tiruchirappalli, India"],"affiliations":[{"raw_affiliation_string":"Computer science Engineering, National Institute of Technology, Tiruchirappalli, India","institution_ids":["https://openalex.org/I122964287"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5112721884","display_name":"Shameedha Begum","orcid":null},"institutions":[{"id":"https://openalex.org/I122964287","display_name":"National Institute of Technology Tiruchirappalli","ror":"https://ror.org/047x65e68","country_code":"IN","type":"education","lineage":["https://openalex.org/I122964287"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Shameedha Begum","raw_affiliation_strings":["Computer science Engineering, National Institute of Technology, Tiruchirappalli, India"],"affiliations":[{"raw_affiliation_string":"Computer science Engineering, National Institute of Technology, Tiruchirappalli, India","institution_ids":["https://openalex.org/I122964287"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5012477842","display_name":"N. Ramasubramaniam","orcid":null},"institutions":[{"id":"https://openalex.org/I122964287","display_name":"National Institute of Technology Tiruchirappalli","ror":"https://ror.org/047x65e68","country_code":"IN","type":"education","lineage":["https://openalex.org/I122964287"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"N. Ramasubramaniam","raw_affiliation_strings":["Computer science Engineering, National Institute of Technology, Tiruchirappalli, India"],"affiliations":[{"raw_affiliation_string":"Computer science Engineering, National Institute of Technology, Tiruchirappalli, India","institution_ids":["https://openalex.org/I122964287"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5040217125"],"corresponding_institution_ids":["https://openalex.org/I122964287"],"apc_list":null,"apc_paid":null,"fwci":0.1288,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.46933869,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":93},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/data-retention","display_name":"Data retention","score":0.7870020866394043},{"id":"https://openalex.org/keywords/non-volatile-memory","display_name":"Non-volatile memory","score":0.7606277465820312},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.7444325089454651},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7204089760780334},{"id":"https://openalex.org/keywords/reliability","display_name":"Reliability (semiconductor)","score":0.5857459902763367},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.5592559576034546},{"id":"https://openalex.org/keywords/random-access-memory","display_name":"Random access memory","score":0.5448247790336609},{"id":"https://openalex.org/keywords/magnetoresistive-random-access-memory","display_name":"Magnetoresistive random-access memory","score":0.47972574830055237},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4656814932823181},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.4132646322250366},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3593628406524658},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.3310379981994629},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.2877461314201355}],"concepts":[{"id":"https://openalex.org/C2780866740","wikidata":"https://www.wikidata.org/wiki/Q5227345","display_name":"Data retention","level":2,"score":0.7870020866394043},{"id":"https://openalex.org/C177950962","wikidata":"https://www.wikidata.org/wiki/Q10997658","display_name":"Non-volatile memory","level":2,"score":0.7606277465820312},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.7444325089454651},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7204089760780334},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.5857459902763367},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.5592559576034546},{"id":"https://openalex.org/C2994168587","wikidata":"https://www.wikidata.org/wiki/Q5295","display_name":"Random access memory","level":2,"score":0.5448247790336609},{"id":"https://openalex.org/C46891859","wikidata":"https://www.wikidata.org/wiki/Q1061546","display_name":"Magnetoresistive random-access memory","level":3,"score":0.47972574830055237},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4656814932823181},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.4132646322250366},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3593628406524658},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.3310379981994629},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.2877461314201355},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/rait.2018.8388985","is_oa":false,"landing_page_url":"https://doi.org/10.1109/rait.2018.8388985","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 4th International Conference on Recent Advances in Information Technology (RAIT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.5400000214576721}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":22,"referenced_works":["https://openalex.org/W1984574424","https://openalex.org/W2009792503","https://openalex.org/W2028392777","https://openalex.org/W2064977311","https://openalex.org/W2083066702","https://openalex.org/W2084007230","https://openalex.org/W2097823832","https://openalex.org/W2099550931","https://openalex.org/W2116826022","https://openalex.org/W2125428294","https://openalex.org/W2126938195","https://openalex.org/W2128968239","https://openalex.org/W2135393827","https://openalex.org/W2169875292","https://openalex.org/W2338546029","https://openalex.org/W2360811925","https://openalex.org/W2543205889","https://openalex.org/W2553994426","https://openalex.org/W2603574511","https://openalex.org/W2996954354","https://openalex.org/W4237731417","https://openalex.org/W6884934207"],"related_works":["https://openalex.org/W2110321764","https://openalex.org/W3109940112","https://openalex.org/W1909296377","https://openalex.org/W3133379968","https://openalex.org/W2783549708","https://openalex.org/W2171162600","https://openalex.org/W2585458402","https://openalex.org/W2342993049","https://openalex.org/W2942190539","https://openalex.org/W2810613542"],"abstract_inverted_index":{"Recent":[0],"trends":[1],"on":[2],"Emerging":[3],"Technologies":[4],"of":[5,25,52,56,72,91,124],"Non-Volatile":[6],"Memory":[7,20],"(NVM)":[8],"were":[9],"considered":[10],"as":[11,97],"better":[12],"alternatives":[13],"for":[14],"SRAM.":[15],"Spin-Transfer":[16],"Torque":[17],"Random":[18],"Access":[19],"(STT-RAM)":[21],"is":[22,79,86],"a":[23,50],"type":[24],"NVM":[26,38,92],"having":[27],"less":[28],"leakage":[29],"power":[30],"and":[31,43,128],"high":[32,44],"cell":[33],"density.":[34],"Besides":[35],"its":[36],"advantages,":[37],"has":[39,64,117],"low":[40],"write":[41,71,105],"endurance":[42],"error":[45],"rates.":[46],"This":[47,78],"paper":[48],"proposes":[49],"mechanism":[51],"enhancing":[53],"the":[54,70,82,100,104,110,113,122,125,133,140],"lifetime":[55,123],"STT-RAM.":[57],"The":[58],"Sliding":[59],"mode":[60],"based":[61],"ECC":[62,73,83],"architecture":[63],"been":[65,118],"proposed":[66,111],"to":[67,88,99,120,139],"evenly":[68],"distribute":[69],"bits":[74],"across":[75],"data":[76,101],"bits.":[77],"necessary":[80],"because":[81],"part":[84],"which":[85],"used":[87],"maintain":[89],"reliability":[90],"will":[93],"wear":[94],"out":[95],"early":[96],"compared":[98,138],"part,":[102],"since":[103],"are":[106],"unevenly":[107],"distributed.":[108],"In":[109],"method,":[112],"MRU":[114],"replacement":[115,142],"algorithm":[116],"implemented":[119],"improve":[121],"cache":[126],"block":[127],"it":[129],"was":[130,135],"observed":[131],"that":[132],"improvement":[134],"4x":[136],"when":[137],"LRU":[141],"algorithm.":[143]},"counts_by_year":[{"year":2021,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}