{"id":"https://openalex.org/W2077217824","doi":"https://doi.org/10.1109/rait.2012.6194549","title":"A new approach for high performance and efficient design of CORDIC processor","display_name":"A new approach for high performance and efficient design of CORDIC processor","publication_year":2012,"publication_date":"2012-03-01","ids":{"openalex":"https://openalex.org/W2077217824","doi":"https://doi.org/10.1109/rait.2012.6194549","mag":"2077217824"},"language":"en","primary_location":{"id":"doi:10.1109/rait.2012.6194549","is_oa":false,"landing_page_url":"https://doi.org/10.1109/rait.2012.6194549","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 1st International Conference on Recent Advances in Information Technology (RAIT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5025715526","display_name":"Rohit Jain","orcid":null},"institutions":[{"id":"https://openalex.org/I16292982","display_name":"National Institute of Technology Rourkela","ror":"https://ror.org/011gmn932","country_code":"IN","type":"education","lineage":["https://openalex.org/I16292982"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Rohit Kumar Jain","raw_affiliation_strings":["Department of Electronics & Communication Engineering, National Institute of Technology, Rourkela, India","Department of Electronics and communication Engineering, National Institute of Technology, Rourkela, India-769008"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics & Communication Engineering, National Institute of Technology, Rourkela, India","institution_ids":["https://openalex.org/I16292982"]},{"raw_affiliation_string":"Department of Electronics and communication Engineering, National Institute of Technology, Rourkela, India-769008","institution_ids":["https://openalex.org/I16292982"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5014709016","display_name":"Vijay Kumar Sharma","orcid":"https://orcid.org/0000-0002-5971-1849"},"institutions":[{"id":"https://openalex.org/I16292982","display_name":"National Institute of Technology Rourkela","ror":"https://ror.org/011gmn932","country_code":"IN","type":"education","lineage":["https://openalex.org/I16292982"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"V.K. Sharma","raw_affiliation_strings":["Department of Electronics & Communication Engineering, National Institute of Technology, Rourkela, India","Department of Electronics and communication Engineering, National Institute of Technology, Rourkela, India-769008"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics & Communication Engineering, National Institute of Technology, Rourkela, India","institution_ids":["https://openalex.org/I16292982"]},{"raw_affiliation_string":"Department of Electronics and communication Engineering, National Institute of Technology, Rourkela, India-769008","institution_ids":["https://openalex.org/I16292982"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5073752818","display_name":"Kamalakanta Mahapatra","orcid":"https://orcid.org/0000-0003-4917-7088"},"institutions":[{"id":"https://openalex.org/I16292982","display_name":"National Institute of Technology Rourkela","ror":"https://ror.org/011gmn932","country_code":"IN","type":"education","lineage":["https://openalex.org/I16292982"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"K. K. Mahapatra","raw_affiliation_strings":["Department of Electronics & Communication Engineering, National Institute of Technology, Rourkela, India","Department of Electronics and communication Engineering, National Institute of Technology, Rourkela, India-769008"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics & Communication Engineering, National Institute of Technology, Rourkela, India","institution_ids":["https://openalex.org/I16292982"]},{"raw_affiliation_string":"Department of Electronics and communication Engineering, National Institute of Technology, Rourkela, India-769008","institution_ids":["https://openalex.org/I16292982"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.3473,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.63580289,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"41","issue":null,"first_page":"756","last_page":"760"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9883000254631042,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cordic","display_name":"CORDIC","score":0.9550491571426392},{"id":"https://openalex.org/keywords/datapath","display_name":"Datapath","score":0.8347660303115845},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.7811064720153809},{"id":"https://openalex.org/keywords/subtractor","display_name":"Subtractor","score":0.7693321704864502},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7461297512054443},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7086788415908813},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.5284293293952942},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.4154942035675049},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.39848485589027405},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.36535894870758057},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.36259421706199646},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.15259656310081482},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.07990369200706482}],"concepts":[{"id":"https://openalex.org/C58870171","wikidata":"https://www.wikidata.org/wiki/Q116076","display_name":"CORDIC","level":3,"score":0.9550491571426392},{"id":"https://openalex.org/C2781198647","wikidata":"https://www.wikidata.org/wiki/Q1633673","display_name":"Datapath","level":2,"score":0.8347660303115845},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.7811064720153809},{"id":"https://openalex.org/C187805909","wikidata":"https://www.wikidata.org/wiki/Q1142401","display_name":"Subtractor","level":4,"score":0.7693321704864502},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7461297512054443},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7086788415908813},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.5284293293952942},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.4154942035675049},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.39848485589027405},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.36535894870758057},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.36259421706199646},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.15259656310081482},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.07990369200706482},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/rait.2012.6194549","is_oa":false,"landing_page_url":"https://doi.org/10.1109/rait.2012.6194549","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 1st International Conference on Recent Advances in Information Technology (RAIT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.5699999928474426,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":22,"referenced_works":["https://openalex.org/W1553238937","https://openalex.org/W1575022128","https://openalex.org/W1985956780","https://openalex.org/W2004354965","https://openalex.org/W2046344231","https://openalex.org/W2088372221","https://openalex.org/W2089607228","https://openalex.org/W2096420311","https://openalex.org/W2098414748","https://openalex.org/W2100437717","https://openalex.org/W2114751576","https://openalex.org/W2115452265","https://openalex.org/W2124907183","https://openalex.org/W2127123597","https://openalex.org/W2133875196","https://openalex.org/W2141634973","https://openalex.org/W2150633168","https://openalex.org/W2156171592","https://openalex.org/W2159593207","https://openalex.org/W2165848356","https://openalex.org/W6633065032","https://openalex.org/W6674676489"],"related_works":["https://openalex.org/W2136026969","https://openalex.org/W2808932713","https://openalex.org/W2387631519","https://openalex.org/W2606491455","https://openalex.org/W2380033012","https://openalex.org/W2541509322","https://openalex.org/W2959321197","https://openalex.org/W2136079444","https://openalex.org/W4206835326","https://openalex.org/W2077217824"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3],"new":[4],"approach":[5,25],"for":[6],"the":[7,28,50,55,107],"high":[8],"performance":[9],"and":[10,85],"hardware":[11],"efficient":[12,36],"design":[13,24],"of":[14,31,38],"coordinate":[15],"rotation":[16],"digital":[17],"computer":[18],"(CORDIC)":[19],"processor":[20],"structure.":[21,98,109],"The":[22,60,75],"proposed":[23,61,76,108],"completely":[26],"eliminates":[27],"ROM":[29],"requirement":[30],"constant":[32],"arctangent":[33],"values.":[34],"Furthermore,":[35],"designs":[37],"carry":[39],"look":[40],"ahead":[41],"adders":[42],"(CLAs),":[43],"exploiting":[44],"one":[45],"input":[46],"as":[47,67,69,94],"constant,":[48],"in":[49,65,70,83,90,106],"angle":[51],"adder/subtractor":[52],"datapath":[53],"speeds-up":[54],"computation":[56],"while":[57],"maintaining":[58],"regularity.":[59],"architecture":[62],"is":[63],"implemented":[64],"FPGA":[66,84],"well":[68],"180nm":[71],"standard":[72,91],"cell":[73,92],"library.":[74],"implementation":[77],"has":[78,103],"about":[79,86],"39%":[80],"delay":[81,88],"improvement":[82,89],"34%":[87],"technology":[93],"compared":[95],"to":[96],"basic":[97],"About":[99],"47%":[100],"power":[101],"savings":[102],"been":[104],"achieved":[105]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}