{"id":"https://openalex.org/W4415399788","doi":"https://doi.org/10.1109/prime66228.2025.11203663","title":"High-Level Design of AC-Coupled Gm-C Biquads for Power-Line Communication","display_name":"High-Level Design of AC-Coupled Gm-C Biquads for Power-Line Communication","publication_year":2025,"publication_date":"2025-09-21","ids":{"openalex":"https://openalex.org/W4415399788","doi":"https://doi.org/10.1109/prime66228.2025.11203663"},"language":null,"primary_location":{"id":"doi:10.1109/prime66228.2025.11203663","is_oa":false,"landing_page_url":"https://doi.org/10.1109/prime66228.2025.11203663","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 20th International Conference on PhD Research in Microelectronics and Electronics (PRIME)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5099470682","display_name":"Iacopo Nannipieri","orcid":null},"institutions":[{"id":"https://openalex.org/I108290504","display_name":"University of Pisa","ror":"https://ror.org/03ad39j10","country_code":"IT","type":"education","lineage":["https://openalex.org/I108290504"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Iacopo Nannipieri","raw_affiliation_strings":["University of Pisa,Department of Information Engineering,Pisa,PI,Italy,56122"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Pisa,Department of Information Engineering,Pisa,PI,Italy,56122","institution_ids":["https://openalex.org/I108290504"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5054858954","display_name":"Francesco Gagliardi","orcid":"https://orcid.org/0000-0002-3158-995X"},"institutions":[{"id":"https://openalex.org/I108290504","display_name":"University of Pisa","ror":"https://ror.org/03ad39j10","country_code":"IT","type":"education","lineage":["https://openalex.org/I108290504"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Francesco Gagliardi","raw_affiliation_strings":["University of Pisa,Department of Information Engineering,Pisa,PI,Italy,56122"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Pisa,Department of Information Engineering,Pisa,PI,Italy,56122","institution_ids":["https://openalex.org/I108290504"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5024031386","display_name":"Michele Dei","orcid":"https://orcid.org/0000-0001-5388-0150"},"institutions":[{"id":"https://openalex.org/I108290504","display_name":"University of Pisa","ror":"https://ror.org/03ad39j10","country_code":"IT","type":"education","lineage":["https://openalex.org/I108290504"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Michele Dei","raw_affiliation_strings":["University of Pisa,Department of Information Engineering,Pisa,PI,Italy,56122"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Pisa,Department of Information Engineering,Pisa,PI,Italy,56122","institution_ids":["https://openalex.org/I108290504"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.25798429,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12146","display_name":"Power Line Communications and Noise","score":0.9921000003814697,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12146","display_name":"Power Line Communications and Noise","score":0.9921000003814697,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11444","display_name":"Electromagnetic Compatibility and Noise Suppression","score":0.9803000092506409,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/digital-biquad-filter","display_name":"Digital biquad filter","score":0.9861999750137329},{"id":"https://openalex.org/keywords/modularity","display_name":"Modularity (biology)","score":0.6603999733924866},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.40470001101493835},{"id":"https://openalex.org/keywords/analogue-filter","display_name":"Analogue filter","score":0.4009999930858612},{"id":"https://openalex.org/keywords/electrical-impedance","display_name":"Electrical impedance","score":0.39320001006126404},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.3797999918460846},{"id":"https://openalex.org/keywords/design-methods","display_name":"Design methods","score":0.3734000027179718},{"id":"https://openalex.org/keywords/modular-design","display_name":"Modular design","score":0.35040000081062317},{"id":"https://openalex.org/keywords/filter","display_name":"Filter (signal processing)","score":0.31869998574256897}],"concepts":[{"id":"https://openalex.org/C14455310","wikidata":"https://www.wikidata.org/wiki/Q5276043","display_name":"Digital biquad filter","level":4,"score":0.9861999750137329},{"id":"https://openalex.org/C2779478453","wikidata":"https://www.wikidata.org/wiki/Q6889748","display_name":"Modularity (biology)","level":2,"score":0.6603999733924866},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5595999956130981},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5264000296592712},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.4049000144004822},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.40470001101493835},{"id":"https://openalex.org/C176046018","wikidata":"https://www.wikidata.org/wiki/Q359205","display_name":"Analogue filter","level":4,"score":0.4009999930858612},{"id":"https://openalex.org/C17829176","wikidata":"https://www.wikidata.org/wiki/Q179043","display_name":"Electrical impedance","level":2,"score":0.39320001006126404},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.3797999918460846},{"id":"https://openalex.org/C138852830","wikidata":"https://www.wikidata.org/wiki/Q2292993","display_name":"Design methods","level":2,"score":0.3734000027179718},{"id":"https://openalex.org/C101468663","wikidata":"https://www.wikidata.org/wiki/Q1620158","display_name":"Modular design","level":2,"score":0.35040000081062317},{"id":"https://openalex.org/C106131492","wikidata":"https://www.wikidata.org/wiki/Q3072260","display_name":"Filter (signal processing)","level":2,"score":0.31869998574256897},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.3172999918460846},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.311599999666214},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.30219998955726624},{"id":"https://openalex.org/C149810388","wikidata":"https://www.wikidata.org/wiki/Q5374873","display_name":"Emulation","level":2,"score":0.29420000314712524},{"id":"https://openalex.org/C133731056","wikidata":"https://www.wikidata.org/wiki/Q4917288","display_name":"Control engineering","level":1,"score":0.2937000095844269},{"id":"https://openalex.org/C31352089","wikidata":"https://www.wikidata.org/wiki/Q3750474","display_name":"Systems design","level":2,"score":0.29170000553131104},{"id":"https://openalex.org/C29074008","wikidata":"https://www.wikidata.org/wiki/Q174925","display_name":"Analogue electronics","level":3,"score":0.2904999852180481},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.287200003862381},{"id":"https://openalex.org/C36390408","wikidata":"https://www.wikidata.org/wiki/Q1163067","display_name":"Digital filter","level":3,"score":0.27869999408721924},{"id":"https://openalex.org/C555008776","wikidata":"https://www.wikidata.org/wiki/Q267298","display_name":"Battery (electricity)","level":3,"score":0.27070000767707825},{"id":"https://openalex.org/C8590192","wikidata":"https://www.wikidata.org/wiki/Q1054694","display_name":"Frequency response","level":2,"score":0.2628999948501587},{"id":"https://openalex.org/C77170095","wikidata":"https://www.wikidata.org/wiki/Q1753188","display_name":"Linearity","level":2,"score":0.26089999079704285},{"id":"https://openalex.org/C32946077","wikidata":"https://www.wikidata.org/wiki/Q618079","display_name":"Network analysis","level":2,"score":0.260699987411499},{"id":"https://openalex.org/C39394816","wikidata":"https://www.wikidata.org/wiki/Q939318","display_name":"RC circuit","level":4,"score":0.2590999901294708},{"id":"https://openalex.org/C85899133","wikidata":"https://www.wikidata.org/wiki/Q557211","display_name":"Active filter","level":3,"score":0.257999986410141}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/prime66228.2025.11203663","is_oa":false,"landing_page_url":"https://doi.org/10.1109/prime66228.2025.11203663","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 20th International Conference on PhD Research in Microelectronics and Electronics (PRIME)","raw_type":"proceedings-article"},{"id":"pmh:oai:arpi.unipi.it:11568/1337747","is_oa":false,"landing_page_url":"https://ieeexplore.ieee.org/abstract/document/11203663","pdf_url":null,"source":{"id":"https://openalex.org/S4377196265","display_name":"CINECA IRIS Institutial research information system (University of Pisa)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I108290504","host_organization_name":"University of Pisa","host_organization_lineage":["https://openalex.org/I108290504"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320334322","display_name":"HORIZON EUROPE Framework Programme","ror":null},{"id":"https://openalex.org/F4320338440","display_name":"HORIZON EUROPE Health","ror":null}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":[],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,81],"high-level":[4],"design":[5,45,69,113],"methodology":[6],"for":[7,13,67,120,128],"AC-coupled":[8],"Gm-C":[9],"biquad":[10,32],"filters":[11],"tailored":[12],"power-line":[14],"communication":[15],"(PLC)":[16],"systems,":[17],"specifically":[18],"addressing":[19],"the":[20,34,39,89,94,99,103],"stringent":[21],"requirements":[22],"of":[23,91,98,107],"battery":[24,76],"monitoring":[25],"applications":[26],"(BMA).":[27],"We":[28],"analyze":[29],"two":[30],"standard":[31],"topologies,":[33,109],"Passive-Feedback":[35],"Biquad":[36,41],"(PFB)":[37],"and":[38,47,65,102,123],"Active-Feedback":[40],"(AFB),":[42],"deriving":[43],"key":[44],"equations":[46],"evaluating":[48],"their":[49],"performance":[50],"characteristics":[51,106],"relevant":[52],"to":[53,80,111],"BMA.":[54],"Focusing":[55],"on":[56],"system-level":[57],"perspective,":[58],"we":[59,87],"explore":[60],"trade-offs":[61],"between":[62],"digital":[63],"tunability":[64],"modularity":[66],"optimizing":[68],"effort":[70],"in":[71],"multichannel":[72],"systems":[73],"where":[74],"different":[75],"modules":[77],"are":[78],"coupled":[79],"shared":[82],"power":[83],"network.":[84],"In":[85],"addition,":[86],"discuss":[88],"impact":[90],"parasitic":[92],"capacitance,":[93],"finite":[95],"output":[96],"resistance":[97],"filter":[100],"transconductors,":[101],"input":[104],"impedance":[105],"both":[108],"leading":[110],"clear":[112],"indications.":[114],"Our":[115],"findings":[116],"offer":[117],"valuable":[118],"insight":[119],"designing":[121],"efficient":[122],"adaptable":[124],"analog":[125],"front-end":[126],"circuits":[127],"pLC":[129],"networks.":[130]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-22T00:00:00"}
