{"id":"https://openalex.org/W2966347221","doi":"https://doi.org/10.1109/prime.2019.8787773","title":"Analysis of a Circuit Primitive for the Reliable Design of Digital Nonlinear Oscillators","display_name":"Analysis of a Circuit Primitive for the Reliable Design of Digital Nonlinear Oscillators","publication_year":2019,"publication_date":"2019-07-01","ids":{"openalex":"https://openalex.org/W2966347221","doi":"https://doi.org/10.1109/prime.2019.8787773","mag":"2966347221"},"language":"en","primary_location":{"id":"doi:10.1109/prime.2019.8787773","is_oa":false,"landing_page_url":"https://doi.org/10.1109/prime.2019.8787773","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 15th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5008376177","display_name":"Tommaso Addabbo","orcid":"https://orcid.org/0000-0003-0168-9404"},"institutions":[{"id":"https://openalex.org/I102064193","display_name":"University of Siena","ror":"https://ror.org/01tevnk56","country_code":"IT","type":"education","lineage":["https://openalex.org/I102064193"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"T. Addabbo","raw_affiliation_strings":["Department of Information Engineering and Mathematics, University of Siena \u2013 Via Roma, Italy"],"affiliations":[{"raw_affiliation_string":"Department of Information Engineering and Mathematics, University of Siena \u2013 Via Roma, Italy","institution_ids":["https://openalex.org/I102064193"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5011072460","display_name":"Ada Fort","orcid":"https://orcid.org/0000-0003-0916-1516"},"institutions":[{"id":"https://openalex.org/I102064193","display_name":"University of Siena","ror":"https://ror.org/01tevnk56","country_code":"IT","type":"education","lineage":["https://openalex.org/I102064193"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"A. Fort","raw_affiliation_strings":["Department of Information Engineering and Mathematics, University of Siena \u2013 Via Roma, Italy"],"affiliations":[{"raw_affiliation_string":"Department of Information Engineering and Mathematics, University of Siena \u2013 Via Roma, Italy","institution_ids":["https://openalex.org/I102064193"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5064640550","display_name":"Riccardo Moretti","orcid":"https://orcid.org/0000-0002-1691-3846"},"institutions":[{"id":"https://openalex.org/I102064193","display_name":"University of Siena","ror":"https://ror.org/01tevnk56","country_code":"IT","type":"education","lineage":["https://openalex.org/I102064193"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"R. Moretti","raw_affiliation_strings":["Department of Information Engineering and Mathematics, University of Siena \u2013 Via Roma, Italy"],"affiliations":[{"raw_affiliation_string":"Department of Information Engineering and Mathematics, University of Siena \u2013 Via Roma, Italy","institution_ids":["https://openalex.org/I102064193"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5076956231","display_name":"Marco Mugnaini","orcid":"https://orcid.org/0000-0002-2410-1581"},"institutions":[{"id":"https://openalex.org/I102064193","display_name":"University of Siena","ror":"https://ror.org/01tevnk56","country_code":"IT","type":"education","lineage":["https://openalex.org/I102064193"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"M. Mugnaini","raw_affiliation_strings":["Department of Information Engineering and Mathematics, University of Siena \u2013 Via Roma, Italy"],"affiliations":[{"raw_affiliation_string":"Department of Information Engineering and Mathematics, University of Siena \u2013 Via Roma, Italy","institution_ids":["https://openalex.org/I102064193"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5006110526","display_name":"Valerio Vignoli","orcid":"https://orcid.org/0000-0003-2509-6566"},"institutions":[{"id":"https://openalex.org/I102064193","display_name":"University of Siena","ror":"https://ror.org/01tevnk56","country_code":"IT","type":"education","lineage":["https://openalex.org/I102064193"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"V. Vignoli","raw_affiliation_strings":["Department of Information Engineering and Mathematics, University of Siena \u2013 Via Roma, Italy"],"affiliations":[{"raw_affiliation_string":"Department of Information Engineering and Mathematics, University of Siena \u2013 Via Roma, Italy","institution_ids":["https://openalex.org/I102064193"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5008376177"],"corresponding_institution_ids":["https://openalex.org/I102064193"],"apc_list":null,"apc_paid":null,"fwci":0.7154,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.71539784,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"189","last_page":"192"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12162","display_name":"Cellular Automata and Applications","score":0.9976000189781189,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.7104629278182983},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6870293021202087},{"id":"https://openalex.org/keywords/decorrelation","display_name":"Decorrelation","score":0.6820343732833862},{"id":"https://openalex.org/keywords/asynchronous-circuit","display_name":"Asynchronous circuit","score":0.6043546795845032},{"id":"https://openalex.org/keywords/heuristic","display_name":"Heuristic","score":0.6014083623886108},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.5980937480926514},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.580761194229126},{"id":"https://openalex.org/keywords/nonlinear-system","display_name":"Nonlinear system","score":0.5342776775360107},{"id":"https://openalex.org/keywords/ring-oscillator","display_name":"Ring oscillator","score":0.4944596290588379},{"id":"https://openalex.org/keywords/stability","display_name":"Stability (learning theory)","score":0.4809345602989197},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4511014521121979},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.43421927094459534},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4121081829071045},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3562115430831909},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.29664748907089233},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.2772331237792969},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.18638640642166138},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.18486231565475464},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.13416066765785217},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.12733647227287292},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.12702015042304993},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.12224522233009338},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.10860559344291687},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.0722942054271698}],"concepts":[{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.7104629278182983},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6870293021202087},{"id":"https://openalex.org/C177860922","wikidata":"https://www.wikidata.org/wiki/Q788608","display_name":"Decorrelation","level":2,"score":0.6820343732833862},{"id":"https://openalex.org/C87695204","wikidata":"https://www.wikidata.org/wiki/Q629971","display_name":"Asynchronous circuit","level":5,"score":0.6043546795845032},{"id":"https://openalex.org/C173801870","wikidata":"https://www.wikidata.org/wiki/Q201413","display_name":"Heuristic","level":2,"score":0.6014083623886108},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.5980937480926514},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.580761194229126},{"id":"https://openalex.org/C158622935","wikidata":"https://www.wikidata.org/wiki/Q660848","display_name":"Nonlinear system","level":2,"score":0.5342776775360107},{"id":"https://openalex.org/C104111718","wikidata":"https://www.wikidata.org/wiki/Q2153973","display_name":"Ring oscillator","level":3,"score":0.4944596290588379},{"id":"https://openalex.org/C112972136","wikidata":"https://www.wikidata.org/wiki/Q7595718","display_name":"Stability (learning theory)","level":2,"score":0.4809345602989197},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4511014521121979},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.43421927094459534},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4121081829071045},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3562115430831909},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.29664748907089233},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2772331237792969},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.18638640642166138},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.18486231565475464},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.13416066765785217},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.12733647227287292},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.12702015042304993},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.12224522233009338},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.10860559344291687},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.0722942054271698},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.0},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/prime.2019.8787773","is_oa":false,"landing_page_url":"https://doi.org/10.1109/prime.2019.8787773","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 15th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)","raw_type":"proceedings-article"},{"id":"pmh:oai:usiena-air.unisi.it:11365/1082745","is_oa":false,"landing_page_url":"http://hdl.handle.net/11365/1082745","pdf_url":null,"source":{"id":"https://openalex.org/S4377196319","display_name":"Use Siena air (University of Siena)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I102064193","host_organization_name":"University of Siena","host_organization_lineage":["https://openalex.org/I102064193"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1588877666","https://openalex.org/W1986590348","https://openalex.org/W2030022595","https://openalex.org/W2055851419","https://openalex.org/W2067235573","https://openalex.org/W2117205818","https://openalex.org/W2132979456","https://openalex.org/W2157652868","https://openalex.org/W2792898086","https://openalex.org/W2799438285","https://openalex.org/W2942596950"],"related_works":["https://openalex.org/W2372402010","https://openalex.org/W2363153189","https://openalex.org/W2243536805","https://openalex.org/W2168857195","https://openalex.org/W4372324531","https://openalex.org/W3152471554","https://openalex.org/W2165946612","https://openalex.org/W2373127312","https://openalex.org/W1592424226","https://openalex.org/W142017057"],"abstract_inverted_index":{"We":[0],"propose":[1,33],"a":[2],"heuristic":[3],"generalized":[4],"modeling":[5],"aiming":[6],"to":[7],"investigate":[8],"relevant":[9],"aspects":[10],"concerning":[11],"the":[12,25,34,49,52],"stability":[13],"of":[14,28,36,51],"circuits":[15],"that":[16,41],"combine":[17],"asynchronous":[18],"digital":[19,39],"gates":[20],"in":[21,42],"feedback":[22],"networks.":[23],"After":[24],"theoretical":[26],"inspection":[27],"some":[29],"specific":[30],"cases,":[31],"we":[32],"design":[35],"novel":[37],"low-complexity":[38],"oscillators,":[40],"FPGAs":[43],"can":[44],"reach":[45],"decorrelation":[46],"times":[47],"half":[48],"ones":[50],"fastest":[53],"Ring":[54],"Oscillator":[55],"obtainable":[56],"following":[57],"conventional":[58],"methods.":[59]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":2},{"year":2020,"cited_by_count":4}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}