{"id":"https://openalex.org/W2964451686","doi":"https://doi.org/10.1109/prime.2019.8787747","title":"FPGA Implementation of Novel Routing Algorithm for Butterfly-Fat-Tree Topology based NoC Design","display_name":"FPGA Implementation of Novel Routing Algorithm for Butterfly-Fat-Tree Topology based NoC Design","publication_year":2019,"publication_date":"2019-07-01","ids":{"openalex":"https://openalex.org/W2964451686","doi":"https://doi.org/10.1109/prime.2019.8787747","mag":"2964451686"},"language":"en","primary_location":{"id":"doi:10.1109/prime.2019.8787747","is_oa":false,"landing_page_url":"https://doi.org/10.1109/prime.2019.8787747","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 15th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5068260121","display_name":"P. Veda Bhanu","orcid":"https://orcid.org/0000-0001-5663-8407"},"institutions":[{"id":"https://openalex.org/I4210101034","display_name":"Birla Institute of Technology and Science - Hyderabad Campus","ror":"https://ror.org/014ctt859","country_code":"IN","type":"education","lineage":["https://openalex.org/I4210101034","https://openalex.org/I74796645"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"P. Veda Bhanu","raw_affiliation_strings":["Department of EEE, BITS-Pilani, Hyderabad campus, Telangana, India - 500078"],"affiliations":[{"raw_affiliation_string":"Department of EEE, BITS-Pilani, Hyderabad campus, Telangana, India - 500078","institution_ids":["https://openalex.org/I4210101034"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5074764660","display_name":"Jagadheesh Samala","orcid":"https://orcid.org/0000-0003-2354-3289"},"institutions":[{"id":"https://openalex.org/I4210101034","display_name":"Birla Institute of Technology and Science - Hyderabad Campus","ror":"https://ror.org/014ctt859","country_code":"IN","type":"education","lineage":["https://openalex.org/I4210101034","https://openalex.org/I74796645"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"S. Jagadheesh","raw_affiliation_strings":["Department of EEE, BITS-Pilani, Hyderabad campus, Telangana, India - 500078"],"affiliations":[{"raw_affiliation_string":"Department of EEE, BITS-Pilani, Hyderabad campus, Telangana, India - 500078","institution_ids":["https://openalex.org/I4210101034"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5051149332","display_name":"Vasanth Bhat","orcid":null},"institutions":[{"id":"https://openalex.org/I4210101034","display_name":"Birla Institute of Technology and Science - Hyderabad Campus","ror":"https://ror.org/014ctt859","country_code":"IN","type":"education","lineage":["https://openalex.org/I4210101034","https://openalex.org/I74796645"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Vasanth Bhat","raw_affiliation_strings":["Department of EEE, BITS-Pilani, Hyderabad campus, Telangana, India - 500078"],"affiliations":[{"raw_affiliation_string":"Department of EEE, BITS-Pilani, Hyderabad campus, Telangana, India - 500078","institution_ids":["https://openalex.org/I4210101034"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103476714","display_name":"Garima Agarwal","orcid":"https://orcid.org/0000-0003-4551-8244"},"institutions":[{"id":"https://openalex.org/I4210101034","display_name":"Birla Institute of Technology and Science - Hyderabad Campus","ror":"https://ror.org/014ctt859","country_code":"IN","type":"education","lineage":["https://openalex.org/I4210101034","https://openalex.org/I74796645"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Garima Agarwal","raw_affiliation_strings":["Department of EEE, BITS-Pilani, Hyderabad campus, Telangana, India - 500078"],"affiliations":[{"raw_affiliation_string":"Department of EEE, BITS-Pilani, Hyderabad campus, Telangana, India - 500078","institution_ids":["https://openalex.org/I4210101034"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5108117366","display_name":"J. Soumya","orcid":"https://orcid.org/0000-0003-0112-8383"},"institutions":[{"id":"https://openalex.org/I4210101034","display_name":"Birla Institute of Technology and Science - Hyderabad Campus","ror":"https://ror.org/014ctt859","country_code":"IN","type":"education","lineage":["https://openalex.org/I4210101034","https://openalex.org/I74796645"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"J Soumya","raw_affiliation_strings":["Department of EEE, BITS-Pilani, Hyderabad campus, Telangana, India - 500078"],"affiliations":[{"raw_affiliation_string":"Department of EEE, BITS-Pilani, Hyderabad campus, Telangana, India - 500078","institution_ids":["https://openalex.org/I4210101034"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5068260121"],"corresponding_institution_ids":["https://openalex.org/I4210101034"],"apc_list":null,"apc_paid":null,"fwci":0.1768,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.52916563,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":93},"biblio":{"volume":"54","issue":null,"first_page":"69","last_page":"72"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.995199978351593,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9868999719619751,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/router","display_name":"Router","score":0.7688559293746948},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.767657995223999},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.7414137125015259},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7028986215591431},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.6552078127861023},{"id":"https://openalex.org/keywords/network-on-a-chip","display_name":"Network on a chip","score":0.5581936240196228},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5145530104637146},{"id":"https://openalex.org/keywords/routing-table","display_name":"Routing table","score":0.48305946588516235},{"id":"https://openalex.org/keywords/tree","display_name":"Tree (set theory)","score":0.43826884031295776},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3909189999103546},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.38315433263778687},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.30499744415283203},{"id":"https://openalex.org/keywords/routing-protocol","display_name":"Routing protocol","score":0.2642226219177246},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.08157354593276978}],"concepts":[{"id":"https://openalex.org/C2775896111","wikidata":"https://www.wikidata.org/wiki/Q642560","display_name":"Router","level":2,"score":0.7688559293746948},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.767657995223999},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.7414137125015259},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7028986215591431},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.6552078127861023},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.5581936240196228},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5145530104637146},{"id":"https://openalex.org/C184896649","wikidata":"https://www.wikidata.org/wiki/Q290066","display_name":"Routing table","level":4,"score":0.48305946588516235},{"id":"https://openalex.org/C113174947","wikidata":"https://www.wikidata.org/wiki/Q2859736","display_name":"Tree (set theory)","level":2,"score":0.43826884031295776},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3909189999103546},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.38315433263778687},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.30499744415283203},{"id":"https://openalex.org/C104954878","wikidata":"https://www.wikidata.org/wiki/Q1648707","display_name":"Routing protocol","level":3,"score":0.2642226219177246},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.08157354593276978},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/prime.2019.8787747","is_oa":false,"landing_page_url":"https://doi.org/10.1109/prime.2019.8787747","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 15th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W155863923","https://openalex.org/W2056600407","https://openalex.org/W2091518118","https://openalex.org/W2098156582","https://openalex.org/W2108944341","https://openalex.org/W2116251583","https://openalex.org/W2119677480","https://openalex.org/W2123184444","https://openalex.org/W2125662502","https://openalex.org/W2154323564","https://openalex.org/W2159169758","https://openalex.org/W2160642395","https://openalex.org/W2554621958"],"related_works":["https://openalex.org/W2387264083","https://openalex.org/W2019530156","https://openalex.org/W2604877941","https://openalex.org/W2390885485","https://openalex.org/W2052816277","https://openalex.org/W2167988973","https://openalex.org/W2481444631","https://openalex.org/W2603824091","https://openalex.org/W2439487276","https://openalex.org/W2560886726"],"abstract_inverted_index":{"This":[0,78],"paper":[1],"presents":[2],"a":[3,17,91],"novel":[4],"routing":[5,18,68],"algorithm":[6,19,40,69],"for":[7,25],"Butterfly-Fat-Tree":[8],"(BFT)":[9],"topology":[10,27],"based":[11,60,93],"Network-on-Chip":[12],"(NoC)":[13],"design.":[14],"It":[15,54],"proposes":[16],"along":[20],"with":[21,82],"router":[22,36,84],"addressing":[23],"scheme":[24],"BFT":[26],"which":[28],"can":[29,79],"be":[30,80],"used":[31],"in":[32,44],"any":[33],"generic":[34],"NoC":[35,83],"architecture.":[37],"The":[38],"proposed":[39,67],"has":[41,55],"been":[42,56],"implemented":[43],"software":[45],"using":[46,52,58],"C,":[47],"followed":[48],"by":[49],"hardware":[50,61,92],"implementation":[51],"Verilog.":[53],"validated":[57],"FPGA":[59],"and":[62],"the":[63,71],"results":[64],"show":[65],"that":[66],"routes":[70],"data":[72],"from":[73],"source":[74],"to":[75,86],"destination":[76],"seamlessly.":[77],"incorporated":[81],"architecture":[85],"verify":[87],"several":[88],"functionalities":[89],"on":[90],"prototype.":[94]},"counts_by_year":[{"year":2021,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
