{"id":"https://openalex.org/W2885809849","doi":"https://doi.org/10.1109/prime.2018.8430363","title":"New Current Mode Wheatstone Bridge Topologies with Intrinsic Linearity","display_name":"New Current Mode Wheatstone Bridge Topologies with Intrinsic Linearity","publication_year":2018,"publication_date":"2018-07-01","ids":{"openalex":"https://openalex.org/W2885809849","doi":"https://doi.org/10.1109/prime.2018.8430363","mag":"2885809849"},"language":"en","primary_location":{"id":"doi:10.1109/prime.2018.8430363","is_oa":false,"landing_page_url":"https://doi.org/10.1109/prime.2018.8430363","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5088205417","display_name":"Leila Safari","orcid":"https://orcid.org/0000-0003-0863-5660"},"institutions":[{"id":"https://openalex.org/I26415053","display_name":"University of L'Aquila","ror":"https://ror.org/01j9p1r26","country_code":"IT","type":"education","lineage":["https://openalex.org/I26415053"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"L. Safari","raw_affiliation_strings":["Department of Industrial and Information Engineering and Economics, University of L\u2019Aquila, Italy","Department of Industrial and Information Engineering and Economics, University of L'Aquila, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Industrial and Information Engineering and Economics, University of L\u2019Aquila, Italy","institution_ids":["https://openalex.org/I26415053"]},{"raw_affiliation_string":"Department of Industrial and Information Engineering and Economics, University of L'Aquila, Italy","institution_ids":["https://openalex.org/I26415053"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5075248275","display_name":"Gianluca Barile","orcid":"https://orcid.org/0000-0003-4937-0398"},"institutions":[{"id":"https://openalex.org/I26415053","display_name":"University of L'Aquila","ror":"https://ror.org/01j9p1r26","country_code":"IT","type":"education","lineage":["https://openalex.org/I26415053"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"G. Barile","raw_affiliation_strings":["Department of Industrial and Information Engineering and Economics, University of L\u2019Aquila, Italy","Department of Industrial and Information Engineering and Economics, University of L'Aquila, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Industrial and Information Engineering and Economics, University of L\u2019Aquila, Italy","institution_ids":["https://openalex.org/I26415053"]},{"raw_affiliation_string":"Department of Industrial and Information Engineering and Economics, University of L'Aquila, Italy","institution_ids":["https://openalex.org/I26415053"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5043525605","display_name":"Vincenzo Stornelli","orcid":"https://orcid.org/0000-0001-7082-9429"},"institutions":[{"id":"https://openalex.org/I26415053","display_name":"University of L'Aquila","ror":"https://ror.org/01j9p1r26","country_code":"IT","type":"education","lineage":["https://openalex.org/I26415053"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"V. Stornelli","raw_affiliation_strings":["Department of Industrial and Information Engineering and Economics, University of L\u2019Aquila, Italy","Department of Industrial and Information Engineering and Economics, University of L'Aquila, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Industrial and Information Engineering and Economics, University of L\u2019Aquila, Italy","institution_ids":["https://openalex.org/I26415053"]},{"raw_affiliation_string":"Department of Industrial and Information Engineering and Economics, University of L'Aquila, Italy","institution_ids":["https://openalex.org/I26415053"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5070509034","display_name":"Giuseppe Ferri","orcid":"https://orcid.org/0000-0002-8060-9558"},"institutions":[{"id":"https://openalex.org/I26415053","display_name":"University of L'Aquila","ror":"https://ror.org/01j9p1r26","country_code":"IT","type":"education","lineage":["https://openalex.org/I26415053"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"G. Ferri","raw_affiliation_strings":["Department of Industrial and Information Engineering and Economics, University of L\u2019Aquila, Italy","Department of Industrial and Information Engineering and Economics, University of L'Aquila, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Industrial and Information Engineering and Economics, University of L\u2019Aquila, Italy","institution_ids":["https://openalex.org/I26415053"]},{"raw_affiliation_string":"Department of Industrial and Information Engineering and Economics, University of L'Aquila, Italy","institution_ids":["https://openalex.org/I26415053"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5001111968","display_name":"Alfiero Leoni","orcid":"https://orcid.org/0000-0002-0066-4216"},"institutions":[{"id":"https://openalex.org/I26415053","display_name":"University of L'Aquila","ror":"https://ror.org/01j9p1r26","country_code":"IT","type":"education","lineage":["https://openalex.org/I26415053"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"A. Leoni","raw_affiliation_strings":["Department of Industrial and Information Engineering and Economics, University of L\u2019Aquila, Italy","Department of Industrial and Information Engineering and Economics, University of L'Aquila, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Industrial and Information Engineering and Economics, University of L\u2019Aquila, Italy","institution_ids":["https://openalex.org/I26415053"]},{"raw_affiliation_string":"Department of Industrial and Information Engineering and Economics, University of L'Aquila, Italy","institution_ids":["https://openalex.org/I26415053"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I26415053"],"apc_list":null,"apc_paid":null,"fwci":1.3379,"has_fulltext":false,"cited_by_count":27,"citation_normalized_percentile":{"value":0.79417298,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"9","last_page":"12"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/wheatstone-bridge","display_name":"Wheatstone bridge","score":0.9085341095924377},{"id":"https://openalex.org/keywords/resistor","display_name":"Resistor","score":0.8486456871032715},{"id":"https://openalex.org/keywords/network-topology","display_name":"Network topology","score":0.7449396848678589},{"id":"https://openalex.org/keywords/nmos-logic","display_name":"NMOS logic","score":0.6356419920921326},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5627143979072571},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5519237518310547},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.5296615958213806},{"id":"https://openalex.org/keywords/linearity","display_name":"Linearity","score":0.4934760332107544},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.49270346760749817},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.4881056249141693},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.47838345170021057},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.44429445266723633},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.415707528591156},{"id":"https://openalex.org/keywords/capacitor","display_name":"Capacitor","score":0.4124056100845337},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.4035762846469879}],"concepts":[{"id":"https://openalex.org/C104713690","wikidata":"https://www.wikidata.org/wiki/Q245133","display_name":"Wheatstone bridge","level":4,"score":0.9085341095924377},{"id":"https://openalex.org/C137488568","wikidata":"https://www.wikidata.org/wiki/Q5321","display_name":"Resistor","level":3,"score":0.8486456871032715},{"id":"https://openalex.org/C199845137","wikidata":"https://www.wikidata.org/wiki/Q145490","display_name":"Network topology","level":2,"score":0.7449396848678589},{"id":"https://openalex.org/C197162436","wikidata":"https://www.wikidata.org/wiki/Q83908","display_name":"NMOS logic","level":4,"score":0.6356419920921326},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5627143979072571},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5519237518310547},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.5296615958213806},{"id":"https://openalex.org/C77170095","wikidata":"https://www.wikidata.org/wiki/Q1753188","display_name":"Linearity","level":2,"score":0.4934760332107544},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.49270346760749817},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.4881056249141693},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.47838345170021057},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.44429445266723633},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.415707528591156},{"id":"https://openalex.org/C52192207","wikidata":"https://www.wikidata.org/wiki/Q5322","display_name":"Capacitor","level":3,"score":0.4124056100845337},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.4035762846469879},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/prime.2018.8430363","is_oa":false,"landing_page_url":"https://doi.org/10.1109/prime.2018.8430363","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8399999737739563,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W1490670090","https://openalex.org/W1970676909","https://openalex.org/W1972147225","https://openalex.org/W1980998318","https://openalex.org/W2010163609","https://openalex.org/W2010649675","https://openalex.org/W2030711374","https://openalex.org/W2110253376","https://openalex.org/W2121859559","https://openalex.org/W2138536318","https://openalex.org/W2171865547","https://openalex.org/W2539539611","https://openalex.org/W2752738152","https://openalex.org/W4253006224","https://openalex.org/W4300839023","https://openalex.org/W6676437803"],"related_works":["https://openalex.org/W4387585193","https://openalex.org/W1937807235","https://openalex.org/W1533071759","https://openalex.org/W3198155484","https://openalex.org/W1984759573","https://openalex.org/W4225792967","https://openalex.org/W2120587197","https://openalex.org/W1656632498","https://openalex.org/W2386653579","https://openalex.org/W4288058137"],"abstract_inverted_index":{"In":[0],"this":[1],"paper":[2],"two":[3,22,33],"new":[4],"topologies":[5,59],"for":[6],"current-mode":[7],"Wheatstone":[8],"bridge":[9],"(CMWB)":[10],"are":[11,19,45,96,135],"presented.":[12,136],"The":[13,40],"circuits,":[14,56],"unlike":[15],"other":[16,103],"CMWB":[17,55],"topologies,":[18],"based":[20],"on":[21,119],"second":[23],"generation":[24],"voltage":[25,70,78],"conveyors":[26],"(VCII)":[27],"as":[28,37],"basic":[29],"building":[30],"blocks":[31],"and":[32,99],"nMOS":[34],"transistors":[35],"operating":[36],"variable":[38],"resistor.":[39],"outputs":[41],"of":[42,49],"both":[43],"circuits":[44],"intrinsically":[46],"linear":[47],"function":[48],"R.":[50],"Compared":[51],"to":[52,110],"previously":[53],"reported":[54],"the":[57,75,108,113,124],"proposed":[58,125],"offer":[60],"several":[61],"advantages.":[62],"Firstly,":[63],"they":[64,87,106],"do":[65,88],"not":[66,89],"require":[67],"any":[68,91],"extra":[69],"buffer":[71],"at":[72],"output":[73,77],"i.e.,":[74],"produced":[76],"can":[79],"be":[80],"directly":[81],"used":[82],"in":[83,102],"practical":[84],"applications.":[85],"Secondly,":[86],"employ":[90],"passive":[92],"resistor":[93],"while":[94],"there":[95],"multiple":[97],"grounded":[98],"floating":[100],"resistors":[101],"CMWBs.":[104],"Thirdly,":[105],"have":[107],"capability":[109],"electronically":[111],"control":[112],"gain":[114],"without":[115],"a":[116],"significant":[117],"impact":[118],"consumed":[120],"power.":[121],"To":[122],"confirm":[123],"theory,":[126],"PSpice":[127],"simulation":[128],"results":[129],"using":[130],"0.35m":[131],"CMOS":[132],"technology":[133],"parameters":[134]},"counts_by_year":[{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":7},{"year":2022,"cited_by_count":6},{"year":2021,"cited_by_count":4},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":6},{"year":2018,"cited_by_count":1}],"updated_date":"2026-06-26T08:34:08.712188","created_date":"2025-10-10T00:00:00"}