{"id":"https://openalex.org/W2885195937","doi":"https://doi.org/10.1109/prime.2018.8430361","title":"Improved class-AB output stage for Sub-1 V fully-differential operational amplifiers","display_name":"Improved class-AB output stage for Sub-1 V fully-differential operational amplifiers","publication_year":2018,"publication_date":"2018-07-01","ids":{"openalex":"https://openalex.org/W2885195937","doi":"https://doi.org/10.1109/prime.2018.8430361","mag":"2885195937"},"language":"en","primary_location":{"id":"doi:10.1109/prime.2018.8430361","is_oa":false,"landing_page_url":"https://doi.org/10.1109/prime.2018.8430361","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5020626961","display_name":"Andrea Ria","orcid":"https://orcid.org/0000-0002-2120-9618"},"institutions":[{"id":"https://openalex.org/I108290504","display_name":"University of Pisa","ror":"https://ror.org/03ad39j10","country_code":"IT","type":"education","lineage":["https://openalex.org/I108290504"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"A. Ria","raw_affiliation_strings":["Dipartimento di Ingegneria, dell\u2019Informazione, University of Pisa, Pisa, Italy","Dipartimento di Ingegneria, dell'Informazione, University of Pisa, Pisa, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dipartimento di Ingegneria, dell\u2019Informazione, University of Pisa, Pisa, Italy","institution_ids":["https://openalex.org/I108290504"]},{"raw_affiliation_string":"Dipartimento di Ingegneria, dell'Informazione, University of Pisa, Pisa, Italy","institution_ids":["https://openalex.org/I108290504"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5028712232","display_name":"Simone Del Cesta","orcid":"https://orcid.org/0000-0002-6405-3043"},"institutions":[{"id":"https://openalex.org/I108290504","display_name":"University of Pisa","ror":"https://ror.org/03ad39j10","country_code":"IT","type":"education","lineage":["https://openalex.org/I108290504"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"S. Del Cesta","raw_affiliation_strings":["Dipartimento di Ingegneria, dell\u2019Informazione, University of Pisa, Pisa, Italy","Dipartimento di Ingegneria, dell'Informazione, University of Pisa, Pisa, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dipartimento di Ingegneria, dell\u2019Informazione, University of Pisa, Pisa, Italy","institution_ids":["https://openalex.org/I108290504"]},{"raw_affiliation_string":"Dipartimento di Ingegneria, dell'Informazione, University of Pisa, Pisa, Italy","institution_ids":["https://openalex.org/I108290504"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5001432278","display_name":"Alessandro Catania","orcid":"https://orcid.org/0000-0001-7242-6228"},"institutions":[{"id":"https://openalex.org/I108290504","display_name":"University of Pisa","ror":"https://ror.org/03ad39j10","country_code":"IT","type":"education","lineage":["https://openalex.org/I108290504"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"A. Catania","raw_affiliation_strings":["Dipartimento di Ingegneria, dell\u2019Informazione, University of Pisa, Pisa, Italy","Dipartimento di Ingegneria, dell'Informazione, University of Pisa, Pisa, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dipartimento di Ingegneria, dell\u2019Informazione, University of Pisa, Pisa, Italy","institution_ids":["https://openalex.org/I108290504"]},{"raw_affiliation_string":"Dipartimento di Ingegneria, dell'Informazione, University of Pisa, Pisa, Italy","institution_ids":["https://openalex.org/I108290504"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5080172474","display_name":"Massimo Piotto","orcid":"https://orcid.org/0000-0002-0197-3686"},"institutions":[{"id":"https://openalex.org/I108290504","display_name":"University of Pisa","ror":"https://ror.org/03ad39j10","country_code":"IT","type":"education","lineage":["https://openalex.org/I108290504"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"M. Piotto","raw_affiliation_strings":["Dipartimento di Ingegneria, dell\u2019Informazione, University of Pisa, Pisa, Italy","Dipartimento di Ingegneria, dell'Informazione, University of Pisa, Pisa, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dipartimento di Ingegneria, dell\u2019Informazione, University of Pisa, Pisa, Italy","institution_ids":["https://openalex.org/I108290504"]},{"raw_affiliation_string":"Dipartimento di Ingegneria, dell'Informazione, University of Pisa, Pisa, Italy","institution_ids":["https://openalex.org/I108290504"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5048786468","display_name":"Paolo Bruschi","orcid":"https://orcid.org/0000-0003-2073-1073"},"institutions":[{"id":"https://openalex.org/I108290504","display_name":"University of Pisa","ror":"https://ror.org/03ad39j10","country_code":"IT","type":"education","lineage":["https://openalex.org/I108290504"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"P. Bruschi","raw_affiliation_strings":["Dipartimento di Ingegneria, dell\u2019Informazione, University of Pisa, Pisa, Italy","Dipartimento di Ingegneria, dell'Informazione, University of Pisa, Pisa, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dipartimento di Ingegneria, dell\u2019Informazione, University of Pisa, Pisa, Italy","institution_ids":["https://openalex.org/I108290504"]},{"raw_affiliation_string":"Dipartimento di Ingegneria, dell'Informazione, University of Pisa, Pisa, Italy","institution_ids":["https://openalex.org/I108290504"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I108290504"],"apc_list":null,"apc_paid":null,"fwci":0.2164,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.51476567,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9951000213623047,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11021","display_name":"ECG Monitoring and Analysis","score":0.9940999746322632,"subfield":{"id":"https://openalex.org/subfields/2705","display_name":"Cardiology and Cardiovascular Medicine"},"field":{"id":"https://openalex.org/fields/27","display_name":"Medicine"},"domain":{"id":"https://openalex.org/domains/4","display_name":"Health Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/operational-amplifier","display_name":"Operational amplifier","score":0.6627783179283142},{"id":"https://openalex.org/keywords/capacitor","display_name":"Capacitor","score":0.6621131896972656},{"id":"https://openalex.org/keywords/amplifier","display_name":"Amplifier","score":0.6321579813957214},{"id":"https://openalex.org/keywords/differential-amplifier","display_name":"Differential amplifier","score":0.5501759648323059},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.5423880219459534},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.529535174369812},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.5140877366065979},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.489596426486969},{"id":"https://openalex.org/keywords/switched-capacitor","display_name":"Switched capacitor","score":0.45681700110435486},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.44651851058006287},{"id":"https://openalex.org/keywords/class","display_name":"Class (philosophy)","score":0.4325181543827057},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.42835694551467896},{"id":"https://openalex.org/keywords/current","display_name":"Current (fluid)","score":0.42745715379714966},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.41613495349884033},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.38855957984924316},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2679870128631592},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.154558002948761}],"concepts":[{"id":"https://openalex.org/C145366948","wikidata":"https://www.wikidata.org/wiki/Q178947","display_name":"Operational amplifier","level":4,"score":0.6627783179283142},{"id":"https://openalex.org/C52192207","wikidata":"https://www.wikidata.org/wiki/Q5322","display_name":"Capacitor","level":3,"score":0.6621131896972656},{"id":"https://openalex.org/C194257627","wikidata":"https://www.wikidata.org/wiki/Q211554","display_name":"Amplifier","level":3,"score":0.6321579813957214},{"id":"https://openalex.org/C11722477","wikidata":"https://www.wikidata.org/wiki/Q1056298","display_name":"Differential amplifier","level":4,"score":0.5501759648323059},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.5423880219459534},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.529535174369812},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.5140877366065979},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.489596426486969},{"id":"https://openalex.org/C103357873","wikidata":"https://www.wikidata.org/wiki/Q572656","display_name":"Switched capacitor","level":4,"score":0.45681700110435486},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.44651851058006287},{"id":"https://openalex.org/C2777212361","wikidata":"https://www.wikidata.org/wiki/Q5127848","display_name":"Class (philosophy)","level":2,"score":0.4325181543827057},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.42835694551467896},{"id":"https://openalex.org/C148043351","wikidata":"https://www.wikidata.org/wiki/Q4456944","display_name":"Current (fluid)","level":2,"score":0.42745715379714966},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.41613495349884033},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.38855957984924316},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2679870128631592},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.154558002948761},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/prime.2018.8430361","is_oa":false,"landing_page_url":"https://doi.org/10.1109/prime.2018.8430361","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","raw_type":"proceedings-article"},{"id":"pmh:oai:arpi.unipi.it:11568/946422","is_oa":false,"landing_page_url":"http://hdl.handle.net/11568/946422","pdf_url":null,"source":{"id":"https://openalex.org/S4377196265","display_name":"CINECA IRIS Institutial research information system (University of Pisa)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I108290504","host_organization_name":"University of Pisa","host_organization_lineage":["https://openalex.org/I108290504"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.8199999928474426,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1551666193","https://openalex.org/W1672697766","https://openalex.org/W1997902048","https://openalex.org/W2112611349","https://openalex.org/W2125337150","https://openalex.org/W2142100952","https://openalex.org/W2164148798","https://openalex.org/W2770669040","https://openalex.org/W4285719527"],"related_works":["https://openalex.org/W2124313625","https://openalex.org/W2259288840","https://openalex.org/W3141909902","https://openalex.org/W2181720916","https://openalex.org/W2546195600","https://openalex.org/W2129228928","https://openalex.org/W2029273722","https://openalex.org/W1550906089","https://openalex.org/W2072566428","https://openalex.org/W3046374476"],"abstract_inverted_index":{"An":[0],"existent":[1],"architecture":[2],"for":[3,14,70],"low":[4],"voltage":[5,42],"class-AB":[6,32],"output":[7,49],"stages":[8],"is":[9,108],"analyzed":[10],"finding":[11],"critical":[12],"issues":[13],"which":[15],"effective":[16],"original":[17],"solutions":[18],"are":[19,82],"proposed.":[20],"The":[21,62,77,101],"approach":[22],"has":[23],"been":[24],"applied":[25],"to":[26],"the":[27,80,95,106],"design":[28],"of":[29,37,43,51,58,79,86,105],"a":[30,40,47,66,91],"compact":[31],"fully-differential":[33],"operational":[34],"amplifier,":[35],"capable":[36],"operating":[38],"at":[39],"supply":[41,60],"0.8":[44],"V,":[45],"providing":[46],"maximum":[48],"current":[50],"7.5":[52],"mA":[53],"with":[54,94],"only":[55],"156":[56],"uA":[57],"quiescent":[59],"current.":[61],"proposed":[63],"amplifier":[64,81],"constitutes":[65],"convenient":[67],"building":[68],"block":[69],"switched-capacitor":[71],"circuits":[72],"and":[73],"low-voltage":[74],"sensor":[75],"interfaces.":[76],"performances":[78],"demonstrated":[83],"by":[84],"means":[85],"electrical":[87],"simulations":[88],"performed":[89],"on":[90],"prototype":[92],"designed":[93],"UMC":[96],"0.18":[97],"um":[98],"CMOS":[99],"process.":[100],"total":[102],"estimated":[103],"area":[104],"cell":[107],"0.023":[109],"mm":[110],"<sup":[111],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[112],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[113],".":[114]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1}],"updated_date":"2026-07-02T09:51:11.867554","created_date":"2025-10-10T00:00:00"}