{"id":"https://openalex.org/W2127745296","doi":"https://doi.org/10.1109/prdc.2004.1276550","title":"Cache scrubbing in microprocessors: myth or necessity?","display_name":"Cache scrubbing in microprocessors: myth or necessity?","publication_year":2004,"publication_date":"2004-06-10","ids":{"openalex":"https://openalex.org/W2127745296","doi":"https://doi.org/10.1109/prdc.2004.1276550","mag":"2127745296"},"language":"en","primary_location":{"id":"doi:10.1109/prdc.2004.1276550","is_oa":false,"landing_page_url":"https://doi.org/10.1109/prdc.2004.1276550","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"10th IEEE Pacific Rim International Symposium on Dependable Computing, 2004. Proceedings.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5087813577","display_name":"S. Mukherjee","orcid":"https://orcid.org/0000-0002-2750-5071"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"S.S. Mukherjee","raw_affiliation_strings":["Massachusetts Microprocessor Design Center, Intel Corporation, Shrewsbury, MA, USA"],"affiliations":[{"raw_affiliation_string":"Massachusetts Microprocessor Design Center, Intel Corporation, Shrewsbury, MA, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5024384625","display_name":"Joel Emer","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"J. Emer","raw_affiliation_strings":["Massachusetts Microprocessor Design Center, Intel Corporation, Shrewsbury, MA, USA"],"affiliations":[{"raw_affiliation_string":"Massachusetts Microprocessor Design Center, Intel Corporation, Shrewsbury, MA, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5074638026","display_name":"Tryggve Fossum","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"T. Fossum","raw_affiliation_strings":["Massachusetts Microprocessor Design Center, Intel Corporation, Shrewsbury, MA, USA"],"affiliations":[{"raw_affiliation_string":"Massachusetts Microprocessor Design Center, Intel Corporation, Shrewsbury, MA, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5108353805","display_name":"S.K. Reinhardt","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]},{"id":"https://openalex.org/I27837315","display_name":"University of Michigan\u2013Ann Arbor","ror":"https://ror.org/00jmfr291","country_code":"US","type":"education","lineage":["https://openalex.org/I27837315"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"S.K. Reinhardt","raw_affiliation_strings":["Advanced Computer Architecture Laboratory, EECS Department, University of Michigan, Ann Arbor, MI, USA","Massachusetts Microprocessor Design Center, Intel Corporation, Shrewsbury, MA, USA"],"affiliations":[{"raw_affiliation_string":"Advanced Computer Architecture Laboratory, EECS Department, University of Michigan, Ann Arbor, MI, USA","institution_ids":["https://openalex.org/I27837315"]},{"raw_affiliation_string":"Massachusetts Microprocessor Design Center, Intel Corporation, Shrewsbury, MA, USA","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5087813577"],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":6.0981,"has_fulltext":false,"cited_by_count":134,"citation_normalized_percentile":{"value":0.96540398,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"37","last_page":"42"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8060081005096436},{"id":"https://openalex.org/keywords/soft-error","display_name":"Soft error","score":0.7399042844772339},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.6321930289268494},{"id":"https://openalex.org/keywords/error-detection-and-correction","display_name":"Error detection and correction","score":0.560482919216156},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.5561262965202332},{"id":"https://openalex.org/keywords/bit-error-rate","display_name":"Bit error rate","score":0.5285314917564392},{"id":"https://openalex.org/keywords/data-scrubbing","display_name":"Data scrubbing","score":0.49486058950424194},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.46611860394477844},{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.43021726608276367},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.42739182710647583},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.40864384174346924},{"id":"https://openalex.org/keywords/decoding-methods","display_name":"Decoding methods","score":0.2806331515312195},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.22141629457473755},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.12789195775985718},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.11152532696723938},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.068977952003479}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8060081005096436},{"id":"https://openalex.org/C154474529","wikidata":"https://www.wikidata.org/wiki/Q1658917","display_name":"Soft error","level":2,"score":0.7399042844772339},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.6321930289268494},{"id":"https://openalex.org/C103088060","wikidata":"https://www.wikidata.org/wiki/Q1062839","display_name":"Error detection and correction","level":2,"score":0.560482919216156},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.5561262965202332},{"id":"https://openalex.org/C56296756","wikidata":"https://www.wikidata.org/wiki/Q840922","display_name":"Bit error rate","level":3,"score":0.5285314917564392},{"id":"https://openalex.org/C89529581","wikidata":"https://www.wikidata.org/wiki/Q5227348","display_name":"Data scrubbing","level":2,"score":0.49486058950424194},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.46611860394477844},{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.43021726608276367},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.42739182710647583},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.40864384174346924},{"id":"https://openalex.org/C57273362","wikidata":"https://www.wikidata.org/wiki/Q576722","display_name":"Decoding methods","level":2,"score":0.2806331515312195},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.22141629457473755},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.12789195775985718},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.11152532696723938},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.068977952003479}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/prdc.2004.1276550","is_oa":false,"landing_page_url":"https://doi.org/10.1109/prdc.2004.1276550","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"10th IEEE Pacific Rim International Symposium on Dependable Computing, 2004. Proceedings.","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.95.5727","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.95.5727","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://pages.cs.wisc.edu/~shubu/papers/cachescrub-prdc2004.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/16","score":0.4699999988079071,"display_name":"Peace, Justice and strong institutions"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1500893261","https://openalex.org/W1819167510","https://openalex.org/W1821730155","https://openalex.org/W2033346530","https://openalex.org/W2105145734","https://openalex.org/W2116097016","https://openalex.org/W2124536119","https://openalex.org/W2127178251","https://openalex.org/W2130280658","https://openalex.org/W2144512449","https://openalex.org/W2169213530","https://openalex.org/W3008392966","https://openalex.org/W4249144718"],"related_works":["https://openalex.org/W2112096947","https://openalex.org/W2806943059","https://openalex.org/W1579918296","https://openalex.org/W167580156","https://openalex.org/W2167435539","https://openalex.org/W2371841116","https://openalex.org/W2786243643","https://openalex.org/W2794208964","https://openalex.org/W2768924083","https://openalex.org/W3026432130"],"abstract_inverted_index":{"Transient":[0],"faults":[1],"from":[2],"neutron":[3],"and":[4,37,102],"alpha":[5],"particle":[6],"strikes":[7,45],"in":[8,52,94,111],"large":[9,125],"SRAM":[10],"caches":[11,126],"have":[12],"become":[13],"a":[14,60,143],"major":[15],"problem":[16],"for":[17,83],"microprocessor":[18],"designers.":[19],"To":[20],"protect":[21],"these":[22],"caches,":[23],"designers":[24],"often":[25],"use":[26],"error":[27,35,39,96,119,140],"correcting":[28],"codes":[29],"(ECC),":[30],"which":[31,95],"typically":[32],"provide":[33],"single-bit":[34,104],"correction":[36],"double-bit":[38,62,85,139],"detection":[40],"(SECDED).":[41],"Unfortunately,":[42],"two":[43,49],"separate":[44],"could":[46],"still":[47],"flip":[48],"different":[50],"bits":[51],"the":[53,78,137],"same":[54],"ECC-protected":[55],"word.":[56],"This":[57],"we":[58,88],"call":[59],"temporal":[61,84,138],"error.":[63],"SECDED":[64],"ECC":[65],"can":[66,107],"only":[67,123],"detect,":[68],"not":[69],"correct":[70],"such":[71,109],"errors.":[72,86],"We":[73],"show":[74,89],"how":[75,90],"to":[76,81,131,135,142],"compute":[77],"mean":[79],"time":[80],"failure":[82],"Additionally,":[87],"fixed-interval":[91],"scrubbing":[92,134],"-":[93,106],"checkers":[97],"periodically":[98],"access":[99],"cache":[100],"blocks":[101],"remove":[103],"errors":[105,110],"mitigate":[108],"processor":[112],"caches.":[113],"Our":[114],"analysis":[115],"using":[116],"current":[117],"soft":[118],"rates":[120],"shows":[121],"that":[122],"very":[124],"(e.g.,":[127],"hundreds":[128],"of":[129],"megabytes":[130],"gigabytes)":[132],"need":[133],"reduce":[136],"rate":[141],"tolerable":[144],"range.":[145]},"counts_by_year":[{"year":2025,"cited_by_count":3},{"year":2024,"cited_by_count":3},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":4},{"year":2019,"cited_by_count":4},{"year":2018,"cited_by_count":4},{"year":2017,"cited_by_count":10},{"year":2016,"cited_by_count":10},{"year":2015,"cited_by_count":9},{"year":2014,"cited_by_count":10},{"year":2013,"cited_by_count":7},{"year":2012,"cited_by_count":10}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}