{"id":"https://openalex.org/W2144859255","doi":"https://doi.org/10.1109/pcee.2000.873617","title":"Application of partitioning methods for the design of parallel programs for a system of digital signal processors","display_name":"Application of partitioning methods for the design of parallel programs for a system of digital signal processors","publication_year":2002,"publication_date":"2002-11-07","ids":{"openalex":"https://openalex.org/W2144859255","doi":"https://doi.org/10.1109/pcee.2000.873617","mag":"2144859255"},"language":"en","primary_location":{"id":"doi:10.1109/pcee.2000.873617","is_oa":false,"landing_page_url":"https://doi.org/10.1109/pcee.2000.873617","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings International Conference on Parallel Computing in Electrical Engineering. PARELEC 2000","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5074136321","display_name":"Mathias Kortke","orcid":null},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"TU Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"M. Kortke","raw_affiliation_strings":["Faculty of Electrical Engineering, Institute of Circuits and Systems, Dresden University of Technology, Dresden, Germany"],"affiliations":[{"raw_affiliation_string":"Faculty of Electrical Engineering, Institute of Circuits and Systems, Dresden University of Technology, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5001897862","display_name":"Thomas Schmitt","orcid":"https://orcid.org/0000-0002-9241-5208"},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"TU Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"T. Schmitt","raw_affiliation_strings":["Faculty of Electrical Engineering, Institute of Circuits and Systems, Dresden University of Technology, Dresden, Germany"],"affiliations":[{"raw_affiliation_string":"Faculty of Electrical Engineering, Institute of Circuits and Systems, Dresden University of Technology, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5007941239","display_name":"Renate Merker","orcid":null},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"TU Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"R. Merker","raw_affiliation_strings":["Faculty of Electrical Engineering, Institute of Circuits and Systems, Dresden University of Technology, Dresden, Germany"],"affiliations":[{"raw_affiliation_string":"Faculty of Electrical Engineering, Institute of Circuits and Systems, Dresden University of Technology, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5074136321"],"corresponding_institution_ids":["https://openalex.org/I78650965"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.19583886,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"139","last_page":"143"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8024142980575562},{"id":"https://openalex.org/keywords/digital-signal-processor","display_name":"Digital signal processor","score":0.723891019821167},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6633169651031494},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.5120146870613098},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.5025138854980469},{"id":"https://openalex.org/keywords/parallel-algorithm","display_name":"Parallel algorithm","score":0.4937802255153656},{"id":"https://openalex.org/keywords/parallel-processing","display_name":"Parallel processing","score":0.45600661635398865},{"id":"https://openalex.org/keywords/digital-signal","display_name":"Digital signal","score":0.4381582736968994},{"id":"https://openalex.org/keywords/signal","display_name":"SIGNAL (programming language)","score":0.435860276222229},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4287011921405792},{"id":"https://openalex.org/keywords/parallel-architecture","display_name":"Parallel architecture","score":0.41958966851234436},{"id":"https://openalex.org/keywords/signal-processing","display_name":"Signal processing","score":0.41430631279945374},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.3867887854576111},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3332022726535797},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.0907122790813446}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8024142980575562},{"id":"https://openalex.org/C161611012","wikidata":"https://www.wikidata.org/wiki/Q106370","display_name":"Digital signal processor","level":3,"score":0.723891019821167},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6633169651031494},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.5120146870613098},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.5025138854980469},{"id":"https://openalex.org/C120373497","wikidata":"https://www.wikidata.org/wiki/Q1087987","display_name":"Parallel algorithm","level":2,"score":0.4937802255153656},{"id":"https://openalex.org/C106515295","wikidata":"https://www.wikidata.org/wiki/Q26806595","display_name":"Parallel processing","level":2,"score":0.45600661635398865},{"id":"https://openalex.org/C52773712","wikidata":"https://www.wikidata.org/wiki/Q175022","display_name":"Digital signal","level":3,"score":0.4381582736968994},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.435860276222229},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4287011921405792},{"id":"https://openalex.org/C2985918086","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel architecture","level":3,"score":0.41958966851234436},{"id":"https://openalex.org/C104267543","wikidata":"https://www.wikidata.org/wiki/Q208163","display_name":"Signal processing","level":3,"score":0.41430631279945374},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.3867887854576111},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3332022726535797},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0907122790813446},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/pcee.2000.873617","is_oa":false,"landing_page_url":"https://doi.org/10.1109/pcee.2000.873617","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings International Conference on Parallel Computing in Electrical Engineering. PARELEC 2000","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W2004804713","https://openalex.org/W2069424183","https://openalex.org/W2082711009","https://openalex.org/W2107166246","https://openalex.org/W2123169298"],"related_works":["https://openalex.org/W1556297113","https://openalex.org/W2365931855","https://openalex.org/W2113248871","https://openalex.org/W2244686501","https://openalex.org/W2322214226","https://openalex.org/W2067631125","https://openalex.org/W3143121479","https://openalex.org/W2374112065","https://openalex.org/W2127752800","https://openalex.org/W584889777"],"abstract_inverted_index":{"In":[0],"this":[1],"paper,":[2],"the":[3,10,19,51],"application":[4],"of":[5,12,29,46],"partitioning":[6,40],"methods":[7],"developed":[8],"for":[9,18],"design":[11],"parallel":[13,20],"processor":[14],"arrays":[15],"is":[16,26],"examined":[17],"program":[21],"generation.":[22],"The":[23,39],"target":[24],"architecture":[25],"a":[27,47],"system":[28],"digital":[30],"signal":[31],"processors":[32],"(DSPs)":[33],"with":[34],"high":[35],"bandwidth":[36],"communication":[37],"channels.":[38],"techniques":[41],"are":[42],"evaluated":[43],"by":[44],"means":[45],"computationally":[48],"intensive":[49],"algorithm:":[50],"tomographic":[52],"reconstruction":[53],"method.":[54]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
