{"id":"https://openalex.org/W2006547947","doi":"https://doi.org/10.1109/pccc.2014.7017091","title":"Analysis of cache tuner architectural layouts for multicore embedded systems","display_name":"Analysis of cache tuner architectural layouts for multicore embedded systems","publication_year":2014,"publication_date":"2014-12-01","ids":{"openalex":"https://openalex.org/W2006547947","doi":"https://doi.org/10.1109/pccc.2014.7017091","mag":"2006547947"},"language":"en","primary_location":{"id":"doi:10.1109/pccc.2014.7017091","is_oa":false,"landing_page_url":"https://doi.org/10.1109/pccc.2014.7017091","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 IEEE 33rd International Performance Computing and Communications Conference (IPCCC)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5075537309","display_name":"Tosiron Adegbija","orcid":"https://orcid.org/0000-0002-2800-4834"},"institutions":[{"id":"https://openalex.org/I33213144","display_name":"University of Florida","ror":"https://ror.org/02y3ad647","country_code":"US","type":"education","lineage":["https://openalex.org/I33213144"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Tosiron Adegbija","raw_affiliation_strings":["Department of Electrical and Computer Engineering University of Florida, Gainesville, FL, USA","Department of Electrical and Computer Engineering, University of Florida, Gainesville FL, USA 32611"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering University of Florida, Gainesville, FL, USA","institution_ids":["https://openalex.org/I33213144"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Florida, Gainesville FL, USA 32611","institution_ids":["https://openalex.org/I33213144"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102928781","display_name":"Ross Gordon","orcid":"https://orcid.org/0000-0003-1034-8695"},"institutions":[{"id":"https://openalex.org/I33213144","display_name":"University of Florida","ror":"https://ror.org/02y3ad647","country_code":"US","type":"education","lineage":["https://openalex.org/I33213144"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ann Gordon-Ross","raw_affiliation_strings":["Department of Electrical and Computer Engineering University of Florida, Gainesville, FL, USA","Department of Electrical and Computer Engineering, University of Florida, Gainesville FL, USA 32611"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering University of Florida, Gainesville, FL, USA","institution_ids":["https://openalex.org/I33213144"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Florida, Gainesville FL, USA 32611","institution_ids":["https://openalex.org/I33213144"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5060374059","display_name":"Marisha Rawlins","orcid":null},"institutions":[{"id":"https://openalex.org/I174491546","display_name":"University of Trinidad and Tobago","ror":"https://ror.org/03np13864","country_code":"TT","type":"education","lineage":["https://openalex.org/I174491546"]}],"countries":["TT"],"is_corresponding":false,"raw_author_name":"Marisha Rawlins","raw_affiliation_strings":["Republic of Trinidad and Tobago, University of Trinidad and Tobago","Center for Information and Communication Technology, University of Trinidad and Tobago, Republic of Trinidad and Tobago"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Republic of Trinidad and Tobago, University of Trinidad and Tobago","institution_ids":["https://openalex.org/I174491546"]},{"raw_affiliation_string":"Center for Information and Communication Technology, University of Trinidad and Tobago, Republic of Trinidad and Tobago","institution_ids":["https://openalex.org/I174491546"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":11,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"8"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.8289691209793091},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7839154005050659},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.7150765061378479},{"id":"https://openalex.org/keywords/cache-coloring","display_name":"Cache coloring","score":0.6486878395080566},{"id":"https://openalex.org/keywords/smart-cache","display_name":"Smart Cache","score":0.6233949661254883},{"id":"https://openalex.org/keywords/cache-invalidation","display_name":"Cache invalidation","score":0.6206325888633728},{"id":"https://openalex.org/keywords/cache-pollution","display_name":"Cache pollution","score":0.5958371162414551},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.5490475296974182},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.5147418975830078},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5098289847373962},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.48324641585350037},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.41549697518348694},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3464164733886719},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.21282848715782166}],"concepts":[{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.8289691209793091},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7839154005050659},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.7150765061378479},{"id":"https://openalex.org/C201148951","wikidata":"https://www.wikidata.org/wiki/Q5015976","display_name":"Cache coloring","level":4,"score":0.6486878395080566},{"id":"https://openalex.org/C167713795","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"Smart Cache","level":5,"score":0.6233949661254883},{"id":"https://openalex.org/C25536678","wikidata":"https://www.wikidata.org/wiki/Q5015977","display_name":"Cache invalidation","level":5,"score":0.6206325888633728},{"id":"https://openalex.org/C113166858","wikidata":"https://www.wikidata.org/wiki/Q5015981","display_name":"Cache pollution","level":5,"score":0.5958371162414551},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.5490475296974182},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.5147418975830078},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5098289847373962},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.48324641585350037},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.41549697518348694},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3464164733886719},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.21282848715782166}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/pccc.2014.7017091","is_oa":false,"landing_page_url":"https://doi.org/10.1109/pccc.2014.7017091","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 IEEE 33rd International Performance Computing and Communications Conference (IPCCC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.6899999976158142,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1624489350","https://openalex.org/W1967973551","https://openalex.org/W2017889564","https://openalex.org/W2070553643","https://openalex.org/W2097662145","https://openalex.org/W2123985597","https://openalex.org/W2128419576","https://openalex.org/W2139805609","https://openalex.org/W2141103990","https://openalex.org/W2145021036","https://openalex.org/W2166892186","https://openalex.org/W2170806963","https://openalex.org/W3149485789","https://openalex.org/W4238549726","https://openalex.org/W4242554931"],"related_works":["https://openalex.org/W2133489088","https://openalex.org/W2363769136","https://openalex.org/W2114386333","https://openalex.org/W2734782074","https://openalex.org/W2126408955","https://openalex.org/W2098406302","https://openalex.org/W2148571123","https://openalex.org/W2031173804","https://openalex.org/W2115222420","https://openalex.org/W2369103246"],"abstract_inverted_index":{"Due":[0],"to":[1,7,83,105,131],"the":[2,35,44],"memory":[3],"hierarchy's":[4],"large":[5],"contribution":[6],"a":[8,116],"microprocessor's":[9],"total":[10],"power,":[11],"cache":[12,41,45,72,78,85,88,102,119,125,156],"tuning":[13,42,79],"is":[14],"an":[15],"ideal":[16],"method":[17],"for":[18,135,151],"optimizing":[19],"overall":[20],"power":[21,31,52,132,165],"consumption":[22],"in":[23],"embedded":[24,28,58,138],"systems.":[25,139],"Since":[26],"most":[27],"systems":[29,59,107],"are":[30],"and":[32,53,68,95,121,133,148,154,166],"area":[33,54,134,167],"constrained,":[34],"hardware":[36],"and/or":[37],"software":[38],"that":[39,158],"orchestrate":[40],"-":[43,47],"tuner":[46,73,86,89,120,126],"must":[48,91],"not":[49],"impose":[50,70],"significant":[51],"overhead.":[55],"Furthermore,":[56],"as":[57],"increasingly":[60],"trend":[61],"towards":[62],"multicore,":[63],"inter-core":[64],"data":[65],"sharing,":[66],"communication,":[67],"synchronization":[69],"additional":[71,109],"design":[74,90,127],"complexity,":[75],"necessitating":[76],"cross-core":[77],"coordination.":[80],"In":[81,111],"order":[82],"minimize":[84],"overhead,":[87],"consider":[92],"these":[93],"overheads":[94],"scalability.":[96],"Whereas":[97],"prior":[98],"work":[99],"proposes":[100],"low-overhead":[101],"tuners,":[103],"scalability":[104],"multicore":[106,137],"requires":[108],"considerations.":[110],"this":[112],"work,":[113],"we":[114,144],"present":[115],"low-overhead,":[117],"scalable":[118,153],"extensively":[122],"evaluate":[123],"various":[124],"tradeoffs":[128],"with":[129],"respect":[130],"constrained":[136],"Based":[140],"on":[141],"our":[142],"analysis,":[143],"formulate":[145],"valuable":[146],"insights":[147],"designer-assisted":[149],"guidelines":[150],"modeling":[152],"efficient":[155],"tuners":[157],"best":[159],"achieve":[160],"optimization":[161],"goals":[162],"while":[163],"maintaining":[164],"constraints.":[168]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":5},{"year":2016,"cited_by_count":3}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
