{"id":"https://openalex.org/W2167094727","doi":"https://doi.org/10.1109/pccc.2003.1203733","title":"The RR/RR CICQ switch: hardware design for 10-Gbps link speed","display_name":"The RR/RR CICQ switch: hardware design for 10-Gbps link speed","publication_year":2003,"publication_date":"2003-01-01","ids":{"openalex":"https://openalex.org/W2167094727","doi":"https://doi.org/10.1109/pccc.2003.1203733","mag":"2167094727"},"language":"en","primary_location":{"id":"doi:10.1109/pccc.2003.1203733","is_oa":false,"landing_page_url":"https://doi.org/10.1109/pccc.2003.1203733","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Conference Proceedings of the 2003 IEEE International Performance, Computing, and Communications Conference, 2003.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5048013499","display_name":"Kenji Yoshigoe","orcid":null},"institutions":[{"id":"https://openalex.org/I2613432","display_name":"University of South Florida","ror":"https://ror.org/032db5x82","country_code":"US","type":"education","lineage":["https://openalex.org/I2613432"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"K. Yoshigoe","raw_affiliation_strings":["Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA","Department of Computer Science and Engineering, University of South Florida, Tampa, FL, USA"],"affiliations":[{"raw_affiliation_string":"Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA","institution_ids":["https://openalex.org/I2613432"]},{"raw_affiliation_string":"Department of Computer Science and Engineering, University of South Florida, Tampa, FL, USA","institution_ids":["https://openalex.org/I2613432"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5006758953","display_name":"Ken Christensen","orcid":"https://orcid.org/0000-0002-3736-5500"},"institutions":[{"id":"https://openalex.org/I2613432","display_name":"University of South Florida","ror":"https://ror.org/032db5x82","country_code":"US","type":"education","lineage":["https://openalex.org/I2613432"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"K. Christensen","raw_affiliation_strings":["Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA","Department of Computer Science and Engineering, University of South Florida, Tampa, FL, USA"],"affiliations":[{"raw_affiliation_string":"Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA","institution_ids":["https://openalex.org/I2613432"]},{"raw_affiliation_string":"Department of Computer Science and Engineering, University of South Florida, Tampa, FL, USA","institution_ids":["https://openalex.org/I2613432"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5063893187","display_name":"Anoj Jacob","orcid":null},"institutions":[{"id":"https://openalex.org/I33213144","display_name":"University of Florida","ror":"https://ror.org/02y3ad647","country_code":"US","type":"education","lineage":["https://openalex.org/I33213144"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"A. Jacob","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL, USA","institution_ids":["https://openalex.org/I33213144"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5048013499"],"corresponding_institution_ids":["https://openalex.org/I2613432"],"apc_list":null,"apc_paid":null,"fwci":3.2242,"has_fulltext":false,"cited_by_count":32,"citation_normalized_percentile":{"value":0.9335472,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"481","last_page":"485"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9811999797821045,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.970300018787384,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/crossbar-switch","display_name":"Crossbar switch","score":0.7888832092285156},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7201782464981079},{"id":"https://openalex.org/keywords/bottleneck","display_name":"Bottleneck","score":0.6271550059318542},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6207522749900818},{"id":"https://openalex.org/keywords/encoder","display_name":"Encoder","score":0.5609576106071472},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.5065699815750122},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.49032190442085266},{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.4509085416793823},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4434436559677124},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.3265731930732727},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.23095890879631042},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.13444021344184875},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.11102712154388428}],"concepts":[{"id":"https://openalex.org/C29984679","wikidata":"https://www.wikidata.org/wiki/Q1929149","display_name":"Crossbar switch","level":2,"score":0.7888832092285156},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7201782464981079},{"id":"https://openalex.org/C2780513914","wikidata":"https://www.wikidata.org/wiki/Q18210350","display_name":"Bottleneck","level":2,"score":0.6271550059318542},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6207522749900818},{"id":"https://openalex.org/C118505674","wikidata":"https://www.wikidata.org/wiki/Q42586063","display_name":"Encoder","level":2,"score":0.5609576106071472},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.5065699815750122},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.49032190442085266},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.4509085416793823},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4434436559677124},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.3265731930732727},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.23095890879631042},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.13444021344184875},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.11102712154388428},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/pccc.2003.1203733","is_oa":false,"landing_page_url":"https://doi.org/10.1109/pccc.2003.1203733","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Conference Proceedings of the 2003 IEEE International Performance, Computing, and Communications Conference, 2003.","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.8.6024","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.8.6024","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.csee.usf.edu/~christen/ipccc03.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.5099999904632568,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W48185593","https://openalex.org/W1513448402","https://openalex.org/W1914361868","https://openalex.org/W2003346154","https://openalex.org/W2016318026","https://openalex.org/W2111366547","https://openalex.org/W2115112041","https://openalex.org/W2125600099","https://openalex.org/W2126169247","https://openalex.org/W2143246841","https://openalex.org/W2152364251","https://openalex.org/W4285719527","https://openalex.org/W6601971179","https://openalex.org/W6630667541"],"related_works":["https://openalex.org/W2058965144","https://openalex.org/W2164382479","https://openalex.org/W2146343568","https://openalex.org/W98480971","https://openalex.org/W2150291671","https://openalex.org/W1569655464","https://openalex.org/W2891987081","https://openalex.org/W2030843684","https://openalex.org/W2115150433","https://openalex.org/W2364622490"],"abstract_inverted_index":{"The":[0,18,48],"combined":[1],"input":[2,10],"and":[3,29],"crossbar":[4],"queued":[5],"(CICQ)":[6],"switch":[7,12,24,53],"is":[8,33,57],"an":[9,39,83],"buffered":[11],"suitable":[13],"for":[14,26,82],"very":[15],"high-speed":[16],"networks.":[17],"implementation":[19],"feasibility":[20],"of":[21,44,50],"the":[22,58],"CICQ":[23,52],"architecture":[25],"24":[27],"ports":[28],"10-Gbps":[30],"link":[31],"speed":[32],"shown":[34],"in":[35,46],"this":[36],"paper":[37],"with":[38,54],"FPGA-based":[40],"design":[41,74,81],"(estimated":[42],"cost":[43],"$30,000":[45],"mid-2002).":[47],"bottleneck":[49],"a":[51,63],"RR":[55,59,67],"scheduling":[56],"poller.":[60],"We":[61],"develop":[62],"priority":[64],"encoder":[65],"based":[66],"poller":[68],"that":[69],"uses":[70],"feedback":[71],"masking.":[72],"This":[73],"has":[75],"lower":[76],"delay":[77],"than":[78],"any":[79],"known":[80],"FPGA":[84],"implementation.":[85]},"counts_by_year":[{"year":2019,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}