{"id":"https://openalex.org/W2891377697","doi":"https://doi.org/10.1109/patmos.2018.8463998","title":"Blade-OC Asynchronous Resilient Template","display_name":"Blade-OC Asynchronous Resilient Template","publication_year":2018,"publication_date":"2018-07-01","ids":{"openalex":"https://openalex.org/W2891377697","doi":"https://doi.org/10.1109/patmos.2018.8463998","mag":"2891377697"},"language":"en","primary_location":{"id":"doi:10.1109/patmos.2018.8463998","is_oa":false,"landing_page_url":"https://doi.org/10.1109/patmos.2018.8463998","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5071934521","display_name":"Moises Herrera","orcid":null},"institutions":[{"id":"https://openalex.org/I1174212","display_name":"University of Southern California","ror":"https://ror.org/03taz7m60","country_code":"US","type":"education","lineage":["https://openalex.org/I1174212"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Moises Herrera","raw_affiliation_strings":["University of Southern California (USC), Los Angeles, CA, United States"],"affiliations":[{"raw_affiliation_string":"University of Southern California (USC), Los Angeles, CA, United States","institution_ids":["https://openalex.org/I1174212"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101715362","display_name":"Tingyu Wang","orcid":"https://orcid.org/0000-0002-2794-5771"},"institutions":[{"id":"https://openalex.org/I1174212","display_name":"University of Southern California","ror":"https://ror.org/03taz7m60","country_code":"US","type":"education","lineage":["https://openalex.org/I1174212"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Tingyu Wang","raw_affiliation_strings":["University of Southern California (USC), Los Angeles, CA, United States"],"affiliations":[{"raw_affiliation_string":"University of Southern California (USC), Los Angeles, CA, United States","institution_ids":["https://openalex.org/I1174212"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5084205024","display_name":"Peter A. Beerel","orcid":"https://orcid.org/0000-0002-8283-0168"},"institutions":[{"id":"https://openalex.org/I1174212","display_name":"University of Southern California","ror":"https://ror.org/03taz7m60","country_code":"US","type":"education","lineage":["https://openalex.org/I1174212"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Peter A. Beerel","raw_affiliation_strings":["University of Southern California (USC), Los Angeles, CA, United States"],"affiliations":[{"raw_affiliation_string":"University of Southern California (USC), Los Angeles, CA, United States","institution_ids":["https://openalex.org/I1174212"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5071934521"],"corresponding_institution_ids":["https://openalex.org/I1174212"],"apc_list":null,"apc_paid":null,"fwci":0.2575,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.57278567,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"147","last_page":"154"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/datapath","display_name":"Datapath","score":0.891168475151062},{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.8799833655357361},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.756376326084137},{"id":"https://openalex.org/keywords/pipeline","display_name":"Pipeline (software)","score":0.600274384021759},{"id":"https://openalex.org/keywords/asynchronous-circuit","display_name":"Asynchronous circuit","score":0.42674919962882996},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.41811835765838623},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3449660539627075},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3390326499938965},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3294534683227539},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.323292076587677},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1412353813648224},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.10993003845214844},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.1082342267036438},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.1011313796043396},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.09764641523361206},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.08684232831001282}],"concepts":[{"id":"https://openalex.org/C2781198647","wikidata":"https://www.wikidata.org/wiki/Q1633673","display_name":"Datapath","level":2,"score":0.891168475151062},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.8799833655357361},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.756376326084137},{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.600274384021759},{"id":"https://openalex.org/C87695204","wikidata":"https://www.wikidata.org/wiki/Q629971","display_name":"Asynchronous circuit","level":5,"score":0.42674919962882996},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.41811835765838623},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3449660539627075},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3390326499938965},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3294534683227539},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.323292076587677},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1412353813648224},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.10993003845214844},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.1082342267036438},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.1011313796043396},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.09764641523361206},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.08684232831001282},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/patmos.2018.8463998","is_oa":false,"landing_page_url":"https://doi.org/10.1109/patmos.2018.8463998","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":23,"referenced_works":["https://openalex.org/W232434517","https://openalex.org/W1518236483","https://openalex.org/W1527084955","https://openalex.org/W1546526482","https://openalex.org/W1577601633","https://openalex.org/W1969991018","https://openalex.org/W2025340565","https://openalex.org/W2033045135","https://openalex.org/W2047435387","https://openalex.org/W2107103004","https://openalex.org/W2137541450","https://openalex.org/W2147504603","https://openalex.org/W2156667996","https://openalex.org/W2157599364","https://openalex.org/W2528504743","https://openalex.org/W2767796712","https://openalex.org/W4231905827","https://openalex.org/W4244634726","https://openalex.org/W4253929472","https://openalex.org/W6634686777","https://openalex.org/W6681929348","https://openalex.org/W6727693829","https://openalex.org/W6746348176"],"related_works":["https://openalex.org/W1948903516","https://openalex.org/W1993985975","https://openalex.org/W2985738161","https://openalex.org/W2146990170","https://openalex.org/W2187164010","https://openalex.org/W4312516786","https://openalex.org/W2085028021","https://openalex.org/W2138474603","https://openalex.org/W2104167653","https://openalex.org/W2362706271"],"abstract_inverted_index":{"This":[0,58],"paper":[1,59],"introduces":[2],"a":[3,34,65],"novel":[4],"timing-resilient":[5],"asynchronous":[6,21],"bundled-data":[7],"template":[8,12,32],"called":[9],"Blade-OC.":[10],"The":[11],"replaces":[13],"the":[14,31],"synchronous":[15],"global":[16],"clock":[17],"driving":[18],"FFs":[19],"with":[20,45],"controllers":[22],"that":[23],"drive":[24],"error-detecting":[25],"latches.":[26],"Compared":[27],"to":[28],"its":[29],"predecessors,":[30],"supports":[33],"larger":[35],"timing":[36],"resiliency":[37],"window":[38],"(TRW)":[39],"enabling":[40],"higher":[41],"performance":[42,62],"for":[43,64],"designs":[44],"wide":[46],"variations":[47],"in":[48,53],"delay,":[49],"such":[50],"as":[51],"seen":[52],"near":[54],"and":[55],"subthreshold":[56],"computing.":[57],"quantifies":[60],"this":[61],"improvement":[63],"variety":[66],"of":[67],"pipeline":[68],"structures":[69],"assuming":[70],"lognormal":[71],"datapath":[72],"delay":[73],"distributions.":[74]},"counts_by_year":[{"year":2024,"cited_by_count":2},{"year":2020,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}