{"id":"https://openalex.org/W2769035662","doi":"https://doi.org/10.1109/patmos.2017.8106974","title":"Timing modeling at RT-level by separation of design- and stress related aging impacts","display_name":"Timing modeling at RT-level by separation of design- and stress related aging impacts","publication_year":2017,"publication_date":"2017-09-01","ids":{"openalex":"https://openalex.org/W2769035662","doi":"https://doi.org/10.1109/patmos.2017.8106974","mag":"2769035662"},"language":"en","primary_location":{"id":"doi:10.1109/patmos.2017.8106974","is_oa":false,"landing_page_url":"https://doi.org/10.1109/patmos.2017.8106974","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5048440875","display_name":"Nils Koppaetzky","orcid":null},"institutions":[{"id":"https://openalex.org/I202367325","display_name":"Oldenburger Institut f\u00fcr Informatik","ror":"https://ror.org/003sav189","country_code":"DE","type":"facility","lineage":["https://openalex.org/I202367325"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Nils Koppaetzky","raw_affiliation_strings":["OFFIS Institute for Information Technology, Oldenburg, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"OFFIS Institute for Information Technology, Oldenburg, Germany","institution_ids":["https://openalex.org/I202367325"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5065522826","display_name":"Malte Metzdorf","orcid":null},"institutions":[{"id":"https://openalex.org/I202367325","display_name":"Oldenburger Institut f\u00fcr Informatik","ror":"https://ror.org/003sav189","country_code":"DE","type":"facility","lineage":["https://openalex.org/I202367325"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Malte Metzdorf","raw_affiliation_strings":["OFFIS Institute for Information Technology, Oldenburg, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"OFFIS Institute for Information Technology, Oldenburg, Germany","institution_ids":["https://openalex.org/I202367325"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5019523640","display_name":"Reef Eilers","orcid":"https://orcid.org/0000-0001-8964-4969"},"institutions":[{"id":"https://openalex.org/I202367325","display_name":"Oldenburger Institut f\u00fcr Informatik","ror":"https://ror.org/003sav189","country_code":"DE","type":"facility","lineage":["https://openalex.org/I202367325"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Reef Eilers","raw_affiliation_strings":["OFFIS Institute for Information Technology, Oldenburg, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"OFFIS Institute for Information Technology, Oldenburg, Germany","institution_ids":["https://openalex.org/I202367325"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5034866545","display_name":"Domenik Helms","orcid":"https://orcid.org/0000-0001-7326-200X"},"institutions":[{"id":"https://openalex.org/I202367325","display_name":"Oldenburger Institut f\u00fcr Informatik","ror":"https://ror.org/003sav189","country_code":"DE","type":"facility","lineage":["https://openalex.org/I202367325"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Domenik Helms","raw_affiliation_strings":["OFFIS Institute for Information Technology, Oldenburg, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"OFFIS Institute for Information Technology, Oldenburg, Germany","institution_ids":["https://openalex.org/I202367325"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5048688572","display_name":"Wolfgang Nebel","orcid":null},"institutions":[{"id":"https://openalex.org/I129877168","display_name":"Carl von Ossietzky Universit\u00e4t Oldenburg","ror":"https://ror.org/033n9gh91","country_code":"DE","type":"education","lineage":["https://openalex.org/I129877168"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Wolfgang Nebel","raw_affiliation_strings":["University of Oldenburg, Oldenburg, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Oldenburg, Oldenburg, Germany","institution_ids":["https://openalex.org/I129877168"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.15463573,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.6980431079864502},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6620771288871765},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.6417533159255981},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.553507387638092},{"id":"https://openalex.org/keywords/spice","display_name":"Spice","score":0.4848421812057495},{"id":"https://openalex.org/keywords/register-transfer-level","display_name":"Register-transfer level","score":0.48004257678985596},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4336378574371338},{"id":"https://openalex.org/keywords/task","display_name":"Task (project management)","score":0.42392703890800476},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.41757622361183167},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.41694340109825134},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.39000633358955383},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.32715463638305664},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.3224605917930603},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.29842427372932434},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.2922375500202179},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.24597805738449097},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.18580201268196106},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1321357786655426}],"concepts":[{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.6980431079864502},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6620771288871765},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.6417533159255981},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.553507387638092},{"id":"https://openalex.org/C2780077345","wikidata":"https://www.wikidata.org/wiki/Q16891888","display_name":"Spice","level":2,"score":0.4848421812057495},{"id":"https://openalex.org/C34854456","wikidata":"https://www.wikidata.org/wiki/Q1484552","display_name":"Register-transfer level","level":4,"score":0.48004257678985596},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4336378574371338},{"id":"https://openalex.org/C2780451532","wikidata":"https://www.wikidata.org/wiki/Q759676","display_name":"Task (project management)","level":2,"score":0.42392703890800476},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.41757622361183167},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.41694340109825134},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.39000633358955383},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.32715463638305664},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3224605917930603},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.29842427372932434},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2922375500202179},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.24597805738449097},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.18580201268196106},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1321357786655426},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/patmos.2017.8106974","is_oa":false,"landing_page_url":"https://doi.org/10.1109/patmos.2017.8106974","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1789558444","https://openalex.org/W2043186622","https://openalex.org/W2091163742","https://openalex.org/W2097579272","https://openalex.org/W2104114347","https://openalex.org/W2134777311","https://openalex.org/W2141212437","https://openalex.org/W2156601616","https://openalex.org/W2346245685","https://openalex.org/W2541518543","https://openalex.org/W3145030156"],"related_works":["https://openalex.org/W4241206086","https://openalex.org/W2109697164","https://openalex.org/W2543290882","https://openalex.org/W1528726807","https://openalex.org/W2123535323","https://openalex.org/W2120935739","https://openalex.org/W1964556228","https://openalex.org/W2101075828","https://openalex.org/W2348265766","https://openalex.org/W2051008800"],"abstract_inverted_index":{"The":[0,190],"simulation":[1],"of":[2,14,62,96,167,186,204,220,236],"aging":[3,103,136,225,252],"induced":[4],"degradation":[5],"mechanisms":[6],"is":[7,68,81,104,142,231,240],"a":[8,129,155,184,241,245],"challenging":[9],"task":[10],"during":[11],"the":[12,28,40,60,82,123,194,207,212,218,229],"design":[13,146],"digital":[15,150],"systems.":[16],"Parametrical":[17],"degradations":[18,48],"can":[19,35],"be":[20,36,50,114],"handled":[21],"most":[22],"accurately":[23],"at":[24,100,140,181],"TCAD":[25],"level,":[26],"as":[27,106],"physical":[29],"models":[30],"like":[31,120],"[1]":[32],"and":[33,65,92,132,165,170,211,222],"[2]":[34],"implemented":[37],"directly.":[38],"On":[39],"other":[41],"hand,":[42],"timing":[43,94,138,158,196,249],"failures":[44],"caused":[45],"by":[46,116,176,228],"such":[47],"cannot":[49],"assessed":[51],"exactly":[52],"lower":[53],"than":[54],"Register":[55],"Transfer":[56],"Level":[57],"(RTL),":[58],"where":[59],"notion":[61],"clock":[63],"delay":[64],"critical":[66],"paths":[67],"introduced.":[69],"Since":[70],"System-Level":[71],"designers":[72],"have":[73],"no":[74],"influence":[75],"on":[76,174],"device":[77],"level":[78,84,118],"abstractions,":[79],"this":[80],"lowest":[83],"for":[85,135,149,206,251],"them":[86],"to":[87,113,144,163,183],"perform":[88],"optimization.":[89],"However":[90],"accurate":[91,131],"realistic":[93],"estimation":[95,139],"different":[97,178],"component":[98],"designs":[99],"RTL":[101,141,157,182,248],"under":[102],"problematic":[105],"entire":[107],"components":[108],"are":[109,198],"either":[110],"too":[111],"large":[112],"simulated":[115],"circuit":[117],"simulators":[119],"SPICE":[121],"or":[122],"simulations":[124],"become":[125],"unacceptably":[126],"slow.":[127],"Thus":[128],"compact,":[130],"efficient":[133],"model":[134,159,250],"aware":[137],"needed":[143],"support":[145],"technology":[147],"co-optimization":[148],"circuits.":[151,189],"This":[152,239],"work":[153],"evaluates":[154],"new":[156],"concept":[160],"with":[161,201,233],"respect":[162],"accuracy":[164],"capability":[166],"separating":[168],"design-":[169,221],"stress":[171,179,223],"related":[172,224],"impacts":[173,226],"aging,":[175],"applying":[177],"scenarios":[180],"selection":[185],"ISCAS89":[187],"Benchmark":[188],"results":[191],"indicate":[192],"that":[193,217],"modeled":[195],"estimations":[197],"sufficiently":[199],"accurate,":[200],"average":[202,234],"RMS":[203,235],"1.13%":[205],"deviation":[208],"between":[209],"circuit-level":[210],"model.":[213],"Results":[214],"also":[215],"demonstrate":[216],"separation":[219],"provided":[227],"approach":[230],"adequate":[232],"2.06%":[237],"respectively.":[238],"significant":[242],"step":[243],"towards":[244],"black":[246],"box":[247],"assessment.":[253]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}