{"id":"https://openalex.org/W2768607776","doi":"https://doi.org/10.1109/patmos.2017.8106971","title":"\u03bcDMA: An autonomous I/O subsystem for IoT end-nodes","display_name":"\u03bcDMA: An autonomous I/O subsystem for IoT end-nodes","publication_year":2017,"publication_date":"2017-09-01","ids":{"openalex":"https://openalex.org/W2768607776","doi":"https://doi.org/10.1109/patmos.2017.8106971","mag":"2768607776"},"language":"en","primary_location":{"id":"doi:10.1109/patmos.2017.8106971","is_oa":false,"landing_page_url":"https://doi.org/10.1109/patmos.2017.8106971","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5079755983","display_name":"Antonio Pullini","orcid":"https://orcid.org/0000-0001-6709-4214"},"institutions":[{"id":"https://openalex.org/I35440088","display_name":"ETH Zurich","ror":"https://ror.org/05a28rw58","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I35440088"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Antonio Pullini","raw_affiliation_strings":["Integrated Systems Laboratory, ETH Z\u00fcrich, Zurich, Switzerland","Integrated Systems Laboratory, ETH Zurich Gloriastr. 35, 8092 Zurich, Switzerland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Integrated Systems Laboratory, ETH Z\u00fcrich, Zurich, Switzerland","institution_ids":["https://openalex.org/I35440088"]},{"raw_affiliation_string":"Integrated Systems Laboratory, ETH Zurich Gloriastr. 35, 8092 Zurich, Switzerland","institution_ids":["https://openalex.org/I35440088"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5023905268","display_name":"Davide Rossi","orcid":"https://orcid.org/0000-0002-0651-5393"},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Davide Rossi","raw_affiliation_strings":["DEI, University of Bologna, Bologna, Italy","DEI - University of Bologna, Via Risorgimento, 2 - 40136 Bologna, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"DEI, University of Bologna, Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]},{"raw_affiliation_string":"DEI - University of Bologna, Via Risorgimento, 2 - 40136 Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5078686831","display_name":"Germain Haugou","orcid":null},"institutions":[{"id":"https://openalex.org/I35440088","display_name":"ETH Zurich","ror":"https://ror.org/05a28rw58","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I35440088"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Germain Haugou","raw_affiliation_strings":["Integrated Systems Laboratory, ETH Z\u00fcrich, Zurich, Switzerland","Integrated Systems Laboratory, ETH Zurich Gloriastr. 35, 8092 Zurich, Switzerland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Integrated Systems Laboratory, ETH Z\u00fcrich, Zurich, Switzerland","institution_ids":["https://openalex.org/I35440088"]},{"raw_affiliation_string":"Integrated Systems Laboratory, ETH Zurich Gloriastr. 35, 8092 Zurich, Switzerland","institution_ids":["https://openalex.org/I35440088"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5043408422","display_name":"Luca Benini","orcid":"https://orcid.org/0000-0001-8068-3806"},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Luca Benini","raw_affiliation_strings":["DEI, University of Bologna, Bologna, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"DEI, University of Bologna, Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":26,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"8"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9973999857902527,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6952725648880005},{"id":"https://openalex.org/keywords/microcontroller","display_name":"Microcontroller","score":0.6348173022270203},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6281472444534302},{"id":"https://openalex.org/keywords/node","display_name":"Node (physics)","score":0.476739764213562},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.472110390663147},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.4161386787891388},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.15133848786354065},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.11511635780334473}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6952725648880005},{"id":"https://openalex.org/C173018170","wikidata":"https://www.wikidata.org/wiki/Q165678","display_name":"Microcontroller","level":2,"score":0.6348173022270203},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6281472444534302},{"id":"https://openalex.org/C62611344","wikidata":"https://www.wikidata.org/wiki/Q1062658","display_name":"Node (physics)","level":2,"score":0.476739764213562},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.472110390663147},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.4161386787891388},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.15133848786354065},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.11511635780334473},{"id":"https://openalex.org/C66938386","wikidata":"https://www.wikidata.org/wiki/Q633538","display_name":"Structural engineering","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/patmos.2017.8106971","is_oa":false,"landing_page_url":"https://doi.org/10.1109/patmos.2017.8106971","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)","raw_type":"proceedings-article"},{"id":"pmh:oai:cris.unibo.it:11585/653378","is_oa":false,"landing_page_url":"http://hdl.handle.net/11585/653378","pdf_url":null,"source":{"id":"https://openalex.org/S4306402579","display_name":"Archivio istituzionale della ricerca (Alma Mater Studiorum Universit\u00e0 di Bologna)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I4210117483","host_organization_name":"Istituto di Ematologia di Bologna","host_organization_lineage":["https://openalex.org/I4210117483"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.4399999976158142,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":3,"referenced_works":["https://openalex.org/W2114623221","https://openalex.org/W2132829148","https://openalex.org/W2582416884"],"related_works":["https://openalex.org/W4316095964","https://openalex.org/W2383001583","https://openalex.org/W2771395446","https://openalex.org/W3091627987","https://openalex.org/W2147310439","https://openalex.org/W2089988144","https://openalex.org/W1985703800","https://openalex.org/W2347749188","https://openalex.org/W1972388196","https://openalex.org/W2735419558"],"abstract_inverted_index":{"The":[0,171],"Internet":[1],"of":[2,10,42,54,106,139,178,193,205],"Things":[3],"revolution":[4],"requires":[5],"long-battery-lifetime,":[6],"autonomous":[7,75,146],"end-nodes":[8],"capable":[9],"probing":[11],"the":[12,39,43,46,55,86,98,103,107,120,134,191,194,198,202,206],"environment":[13],"from":[14,82],"multiple":[15,83],"sensors":[16,84],"and":[17,24,57,119,136,185],"transmit":[18],"it":[19,35],"wirelessly":[20],"after":[21],"data-fusion,":[22],"recognition,":[23],"classification.":[25],"Duty-cycling":[26],"is":[27,88,100],"a":[28,112,155,161,167,175],"well-known":[29],"approach":[30],"to":[31,37,79,211,215],"extend":[32],"battery":[33],"lifetime:":[34],"allows":[36],"keep":[38],"hardware":[40],"resources":[41,105],"micro-controller":[44],"implementing":[45],"end-node":[47],"(MCUs)":[48],"in":[49,89,93,111,125],"sleep":[50],"mode":[51],"for":[52],"most":[53,71],"time,":[56],"activate":[58],"them":[59],"on-demand":[60],"only":[61,182],"during":[62],"data":[63,81,121,183],"acquisition":[64],"or":[65],"processing":[66,104,122],"phases.":[67],"To":[68],"this":[69,130],"end,":[70],"advanced":[72],"MCUs":[73],"feature":[74],"I/O":[76,96,118,142,147,151,207],"subsystems":[77,97,123],"able":[78],"acquire":[80],"when":[85,180],"CPU":[87],"idle":[90],"state.":[91],"However,":[92],"these":[94],"traditional":[95,216],"interconnect":[99],"shared":[101],"with":[102,154,213],"system,":[108],"both":[109,117],"converging":[110],"single-port":[113],"system":[114,157],"memory.":[115],"Moreover,":[116],"stand":[124],"some":[126],"power":[127,169],"domain.":[128,170],"In":[129],"work":[131],"we":[132,188],"overcome":[133],"bandwidth":[135],"power-management":[137],"limitations":[138],"current":[140],"MCU's":[141],"architectures":[143],"introducing":[144],"an":[145,150],"subsystem":[148,208],"coupling":[149],"DMA":[152],"tightly-coupled":[153],"multi-banked":[156],"memory":[158],"controlled":[159],"by":[160,209],"tiny":[162],"CPU,":[163],"which":[164],"stands":[165],"on":[166,197],"dedicated":[168],"proposed":[172],"architecture":[173],"achieves":[174],"transfer":[176],"efficiency":[177],"84%":[179],"considering":[181],"transfers,":[184],"53%":[186],"if":[187],"consider":[189],"also":[190],"overhead":[192],"runtime":[195],"running":[196],"controlling":[199],"processor,":[200],"reducing":[201],"operating":[203],"frequency":[204],"up":[210],"2.2x":[212],"respect":[214],"MCU":[217],"architectures.":[218]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":5},{"year":2022,"cited_by_count":3},{"year":2021,"cited_by_count":5},{"year":2020,"cited_by_count":4},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":4}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
