{"id":"https://openalex.org/W2188707368","doi":"https://doi.org/10.1109/patmos.2015.7347581","title":"Inferring custom architectures from OpenCL","display_name":"Inferring custom architectures from OpenCL","publication_year":2015,"publication_date":"2015-09-01","ids":{"openalex":"https://openalex.org/W2188707368","doi":"https://doi.org/10.1109/patmos.2015.7347581","mag":"2188707368"},"language":"en","primary_location":{"id":"doi:10.1109/patmos.2015.7347581","is_oa":false,"landing_page_url":"https://doi.org/10.1109/patmos.2015.7347581","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 25th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5074444574","display_name":"Krzysztof K\u0229pa","orcid":"https://orcid.org/0000-0003-0702-9570"},"institutions":[{"id":"https://openalex.org/I859038795","display_name":"Virginia Tech","ror":"https://ror.org/02smfhw86","country_code":"US","type":"education","lineage":["https://openalex.org/I859038795"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Krzysztof Kepa","raw_affiliation_strings":["The Virginia Tech Configurable Computing Laboratory, Blacksburg, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"The Virginia Tech Configurable Computing Laboratory, Blacksburg, USA","institution_ids":["https://openalex.org/I859038795"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111374511","display_name":"Ritesh Soni","orcid":null},"institutions":[{"id":"https://openalex.org/I859038795","display_name":"Virginia Tech","ror":"https://ror.org/02smfhw86","country_code":"US","type":"education","lineage":["https://openalex.org/I859038795"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ritesh Soni","raw_affiliation_strings":["The Virginia Tech Configurable Computing Laboratory Blacksburg, Virginia, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"The Virginia Tech Configurable Computing Laboratory Blacksburg, Virginia, USA","institution_ids":["https://openalex.org/I859038795"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5111933984","display_name":"Peter Athanas","orcid":null},"institutions":[{"id":"https://openalex.org/I859038795","display_name":"Virginia Tech","ror":"https://ror.org/02smfhw86","country_code":"US","type":"education","lineage":["https://openalex.org/I859038795"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Peter Athanas","raw_affiliation_strings":["The Virginia Tech Configurable Computing Laboratory Blacksburg, Virginia, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"The Virginia Tech Configurable Computing Laboratory Blacksburg, Virginia, USA","institution_ids":["https://openalex.org/I859038795"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I859038795"],"apc_list":null,"apc_paid":null,"fwci":0.2041,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.40308714,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"9","last_page":"16"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10743","display_name":"Software Testing and Debugging Techniques","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/1712","display_name":"Software"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7211337089538574},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.477181077003479}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7211337089538574},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.477181077003479}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/patmos.2015.7347581","is_oa":false,"landing_page_url":"https://doi.org/10.1109/patmos.2015.7347581","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 25th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W1968432902","https://openalex.org/W1992519395","https://openalex.org/W2010654381","https://openalex.org/W2078555859","https://openalex.org/W2087064593","https://openalex.org/W2108019747","https://openalex.org/W2131355383","https://openalex.org/W2138336319","https://openalex.org/W2141597697","https://openalex.org/W2153185479","https://openalex.org/W2160126455","https://openalex.org/W2171429297","https://openalex.org/W2185138046","https://openalex.org/W2191327475","https://openalex.org/W2256201213","https://openalex.org/W4246166885","https://openalex.org/W6670031658","https://openalex.org/W6692118107"],"related_works":["https://openalex.org/W4391375266","https://openalex.org/W2748952813","https://openalex.org/W2390279801","https://openalex.org/W2358668433","https://openalex.org/W4396701345","https://openalex.org/W2376932109","https://openalex.org/W2001405890","https://openalex.org/W4396696052","https://openalex.org/W4402327032","https://openalex.org/W2382290278"],"abstract_inverted_index":{"OpenCL":[0,41,51,68,83,111,137],"has":[1],"emerged":[2],"as":[3],"the":[4,10,28,40,76,82,90,97,102,110,125],"de":[5],"facto":[6],"cross-platform":[7],"standard":[8],"in":[9,16],"GPU-based":[11],"HPC":[12,18,142],"computing":[13],"domain.":[14],"However,":[15],"FPGA-based":[17,77,141],"systems,":[19],"OpenCL-to-FPGA":[20],"compilers":[21],"often":[22],"yield":[23],"suboptimal":[24],"results":[25],"due":[26],"to":[27,95,159],"rigid":[29,112],"architecture,":[30],"limited":[31],"shared-memory,":[32],"and":[33,87,114],"non-existent":[34],"inter-work-item":[35],"communication":[36,115],"pathways":[37],"implied":[38],"by":[39],"model.":[42,116],"In":[43],"this":[44],"work,":[45],"a":[46,121,130,152],"methodology":[47],"of":[48,75,89,109,136],"inferring":[49],"application-specific":[50],"\u201cwork-item\u201d":[52],"interfaces":[53],"based":[54],"on":[55,151],"kernel":[56],"code":[57],"analysis":[58],"is":[59,64,93,144,149,157],"explored.":[60],"A":[61,134],"proof-of-concept":[62],"prototype":[63],"implemented":[65],"using":[66],"an":[67],"source-to-source":[69],"translator,":[70],"which":[71],"allows":[72],"automated":[73],"generation":[74],"hardware":[78],"accelerators":[79],"directly":[80],"from":[81],"sources.":[84],"The":[85,104,117],"type":[86],"implementation":[88],"inferred":[91,105],"interface":[92,106],"tailored":[94],"match":[96],"data":[98],"access":[99],"patterns":[100,139],"within":[101],"kernel.":[103],"outperforms":[107],"limitations":[108],"architecture":[113],"presented":[118],"approach":[119,128],"achieves":[120],"\u223230x":[122],"speedup":[123],"over":[124],"generic":[126],"memory-based":[127],"for":[129],"16":[131],"work-items":[132],"application.":[133],"set":[135],"coding":[138],"targeting":[140],"systems":[143],"also":[145],"introduced.":[146],"This":[147],"technique":[148],"demonstrated":[150],"popular":[153],"bioinformatics":[154],"algorithm,":[155],"yet":[156],"applicable":[158],"any":[160],"such":[161],"algorithm":[162],"with":[163],"non-standard":[164],"inter-cell":[165],"communications.":[166]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2016,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}