{"id":"https://openalex.org/W2052557851","doi":"https://doi.org/10.1109/patmos.2014.6951900","title":"A methodology for scaling power dissipation values between different FPGAs","display_name":"A methodology for scaling power dissipation values between different FPGAs","publication_year":2014,"publication_date":"2014-09-01","ids":{"openalex":"https://openalex.org/W2052557851","doi":"https://doi.org/10.1109/patmos.2014.6951900","mag":"2052557851"},"language":"en","primary_location":{"id":"doi:10.1109/patmos.2014.6951900","is_oa":false,"landing_page_url":"https://doi.org/10.1109/patmos.2014.6951900","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 24th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5089398144","display_name":"Axel Reimer","orcid":null},"institutions":[{"id":"https://openalex.org/I202367325","display_name":"Oldenburger Institut f\u00fcr Informatik","ror":"https://ror.org/003sav189","country_code":"DE","type":"facility","lineage":["https://openalex.org/I202367325"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Axel Reimer","raw_affiliation_strings":["OFFIS Research Institute, Oldenburg, Germany","OFFIS Research Institute, D- 26121 Oldenburg, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"OFFIS Research Institute, Oldenburg, Germany","institution_ids":["https://openalex.org/I202367325"]},{"raw_affiliation_string":"OFFIS Research Institute, D- 26121 Oldenburg, Germany","institution_ids":["https://openalex.org/I202367325"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5048688572","display_name":"Wolfgang Nebel","orcid":null},"institutions":[{"id":"https://openalex.org/I129877168","display_name":"Carl von Ossietzky Universit\u00e4t Oldenburg","ror":"https://ror.org/033n9gh91","country_code":"DE","type":"education","lineage":["https://openalex.org/I129877168"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Wolfgang Nebel","raw_affiliation_strings":["University of Oldenburg, Oldenburg, Germany","University of Oldenburg, D- 26121, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Oldenburg, Oldenburg, Germany","institution_ids":["https://openalex.org/I129877168"]},{"raw_affiliation_string":"University of Oldenburg, D- 26121, Germany","institution_ids":["https://openalex.org/I129877168"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.10151589,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"1896","issue":null,"first_page":"1","last_page":"8"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8060908317565918},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7096068859100342},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.6141781806945801},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.6016589403152466},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.5188754200935364},{"id":"https://openalex.org/keywords/dissipation","display_name":"Dissipation","score":0.4996683597564697},{"id":"https://openalex.org/keywords/power-analysis","display_name":"Power analysis","score":0.46088314056396484},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.44639667868614197},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.4384578466415405},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.41967397928237915},{"id":"https://openalex.org/keywords/codec","display_name":"Codec","score":0.41062772274017334},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.34273993968963623},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.26357588171958923},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.2444775104522705},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.13887694478034973},{"id":"https://openalex.org/keywords/cryptography","display_name":"Cryptography","score":0.09758833050727844}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8060908317565918},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7096068859100342},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.6141781806945801},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.6016589403152466},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.5188754200935364},{"id":"https://openalex.org/C135402231","wikidata":"https://www.wikidata.org/wiki/Q898440","display_name":"Dissipation","level":2,"score":0.4996683597564697},{"id":"https://openalex.org/C71743495","wikidata":"https://www.wikidata.org/wiki/Q2845210","display_name":"Power analysis","level":3,"score":0.46088314056396484},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.44639667868614197},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.4384578466415405},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.41967397928237915},{"id":"https://openalex.org/C161765866","wikidata":"https://www.wikidata.org/wiki/Q184748","display_name":"Codec","level":2,"score":0.41062772274017334},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.34273993968963623},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.26357588171958923},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2444775104522705},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.13887694478034973},{"id":"https://openalex.org/C178489894","wikidata":"https://www.wikidata.org/wiki/Q8789","display_name":"Cryptography","level":2,"score":0.09758833050727844},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C97355855","wikidata":"https://www.wikidata.org/wiki/Q11473","display_name":"Thermodynamics","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/patmos.2014.6951900","is_oa":false,"landing_page_url":"https://doi.org/10.1109/patmos.2014.6951900","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 24th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.6200000047683716}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W1943664624","https://openalex.org/W1967128905","https://openalex.org/W1977850862","https://openalex.org/W1998864549","https://openalex.org/W2072453503","https://openalex.org/W2077076315","https://openalex.org/W2090362256","https://openalex.org/W2097798204","https://openalex.org/W2100903835","https://openalex.org/W2108677147","https://openalex.org/W2118014020","https://openalex.org/W2139900512","https://openalex.org/W2143880270","https://openalex.org/W3141589993","https://openalex.org/W3148241561","https://openalex.org/W3149866969","https://openalex.org/W6640881433"],"related_works":["https://openalex.org/W2070693700","https://openalex.org/W2037960874","https://openalex.org/W2097839191","https://openalex.org/W2132107645","https://openalex.org/W3200538824","https://openalex.org/W3005710104","https://openalex.org/W3092334294","https://openalex.org/W2505126014","https://openalex.org/W2014496217","https://openalex.org/W3007361144"],"abstract_inverted_index":{"Power":[0],"dissipation":[1,127],"is":[2,55,72,93,103,128],"one":[3,28,49],"of":[4,29,64,80,98],"the":[5,20,76,123,151,162],"key":[6],"parameters":[7],"when":[8],"designing":[9],"digital":[10],"circuits.":[11],"While":[12],"an":[13,23,41,157],"ASIC":[14],"can":[15,133,146],"be":[16,134,147],"exactly":[17],"fitted":[18],"to":[19,26,52,149],"requirements,":[21],"targeting":[22],"FPGA":[24,50,67,83,155],"means":[25],"select":[27],"many":[30,65],"commercially":[31],"available":[32],"FPGAs":[33,54],"having":[34],"different":[35,66],"power":[36,46,99,126,132,164],"characteristics.":[37],"In":[38],"this":[39],"work":[40],"approach":[42],"for":[43,95,122,156,167],"scaling":[44],"existing":[45,158],"values":[47],"from":[48],"implementation":[51],"other":[53],"presented.":[56],"This":[57],"enables":[58],"a":[59,90,106,111,139],"fast":[60],"design":[61,159],"space":[62],"exploration":[63],"target":[68,154],"architectures.":[69],"The":[70,101,117,144],"methodology":[71,145],"based":[73],"on":[74],"characterising":[75],"most":[77,152],"important":[78],"properties":[79],"each":[81,96],"relevant":[82],"type":[84],"using":[85,105],"some":[86],"test":[87],"designs.":[88,116],"Afterwards,":[89],"modelling":[91],"process":[92],"started":[94],"aspect":[97],"dissipation.":[100],"model":[102],"evaluated":[104],"secure":[107],"hashing":[108],"algorithm":[109],"and":[110],"Viterbi":[112],"codec":[113],"as":[114],"benchmark":[115],"mean":[118,140],"absolute":[119],"relative":[120],"error":[121,141],"total":[124],"dynamic":[125],"7.3%":[129],"while":[130],"static":[131],"modelled":[135],"nearly":[136],"perfectly":[137],"with":[138],"below":[142],"0.01%.":[143],"used":[148],"choose":[150],"power-efficient":[153],"without":[160],"executing":[161],"traditional":[163],"estimation":[165],"flow":[166],"every":[168],"device":[169],"under":[170],"consideration.":[171]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
